Datasheet

PIC16F7X7
DS30498D-page 26  2003-2013 Microchip Technology Inc.
2.2.2.6 PIE2 Register
The PIE2 register contains the individual enable bits for
the CCP2 and CCP3 peripheral interrupts.
REGISTER 2-6: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ADDRESS 8Dh)
R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0
OSFIE CMIE LVDIE
—BCLIE— CCP3IE CCP2IE
bit 7 bit 0
bit 7 OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 6 CMIE: Comparator Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 5 LVDIE: Low-Voltage Detect Interrupt Enable bit
1 = LVD interrupt is enabled
0 = LVD interrupt is disabled
bit 4 Unimplemented: Read as ‘0’
bit 3 BCLIE: Bus Collision Interrupt Enable bit
1 = Enable bus collision interrupt in the SSP when configured for I
2
C Master mode
0 = Disable bus collision interrupt in the SSP when configured for I
2
C Master mode
bit 2 Unimplemented: Read as ‘0’
bit 1 CCP3IE: CCP3 Interrupt Enable bit
1 = Enables the CCP3 interrupt
0 = Disables the CCP3 interrupt
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown