Datasheet

PIC16F7X7
DS30498D-page 232  2003-2013 Microchip Technology Inc.
FIGURE 18-18: AUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 18-13: AUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 18-19: AUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 18-14: AUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Note: Refer to Figure 18-4 for load conditions.
121
121
122
RC6/TX/CK
RC7/RX/DT
pin
pin
120
Param
No.
Symbol Characteristic Min Typ† Max Units Conditions
120 T
CKH2DTV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid PIC16F7X7 — — 80 ns
PIC16LF7X7 — — 100 ns
121 T
CKRF Clock Out Rise Time and Fall Time
(Master mode)
PIC16F7X7 — — 45 ns
PIC16LF7X7 — — 50 ns
122 T
DTRF Data Out Rise Time and Fall Time PIC16F7X7 — — 45 ns
PIC16LF7X7 — — 50 ns
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note: Refer to Figure 18-4 for load conditions.
125
126
RC6/TX/CK
RC7/RX/DT
pin
pin
Param
No.
Symbol Characteristic Min Typ† Max Units Conditions
125 T
DTV2CKL SYNC RCV (MASTER & SLAVE)
Data Setup before CK  (DT setup time) 15 — — ns
126 T
CKL2DTL Data Hold after CK  (DT hold time) 15 — — ns
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.