Datasheet
PIC16F7X7
DS30498D-page 20 2003-2013 Microchip Technology Inc.
Bank 2
100h
(4)
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 30, 180
101h TMR0 Timer0 Module Register xxxx xxxx 76, 180
102h
(4)
PCL Program Counter (PC) Least Significant Byte 0000 0000 29, 180
103h
(4)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 21, 180
104h
(4)
FSR Indirect Data Memory Address Pointer xxxx xxxx 30, 180
105h WDTCON
— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 187
106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx 64, 180
107h — Unimplemented — —
108h — Unimplemented — —
109h LVDCON
— — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 176
10Ah
(1,4)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 23, 180
10Bh
(4)
INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 25, 180
10Ch PMDATA EEPROM Data Register Low Byte xxxx xxxx 32, 181
10Dh PMADR EEPROM Address Register Low Byte xxxx xxxx 32, 181
10Eh PMDATH
— — EEPROM Data Register High Byte --xx xxxx 32, 181
10Fh PMADRH
— — — — EEPROM Address Register High Byte ---- xxxx 32, 181
Bank 3
180h
(4)
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 30, 180
181h
OPTION_REG
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 22, 180
182h
(4)
PCL Program Counter (PC) Least Significant Byte 0000 0000 29, 180
183h
(4)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 21, 180
184h
(4)
FSR Indirect Data Memory Address Pointer xxxx xxxx 30, 180
185h — Unimplemented — —
186h TRISB PORTB Data Direction Register 1111 1111 64, 181
187h — Unimplemented — —
188h — Unimplemented — —
189h — Unimplemented — —
18Ah
(1,4)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 23, 180
18Bh
(4)
INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 25, 180
18Ch PMCON1
r
(6)
— — — — — —RD1--- ---0 32, 181
18Dh — Reserved, maintain clear — —
18Eh — Reserved, maintain clear — —
18Fh — Reserved, maintain clear — —
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Details
on page
Legend: x = unknown, u = unchanged, q = value depends on condition, — = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> bits, whose contents
are transferred to the upper byte of the program counter during branches (CALL or GOTO).
2: Other (non Power-up) Resets include external Reset through MCLR
and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices (except for RE3), read as ‘0’.
6: This bit always reads as a ‘1’.
7: OSCCON<OSTS> bit resets to ‘0’ with dual-speed start-up and LP, HS or HS-PLL selected as the oscillator.
8: RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’.