Datasheet
2003-2013 Microchip Technology Inc. DS30498D-page 19
PIC16F7X7
Bank 1
80h
(4)
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 30, 180
81h
OPTION_REG
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 22, 180
82h
(4)
PCL Program Counter’s (PC) Least Significant Byte 0000 0000 29, 180
83h
(4)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 21, 180
84h
(4)
FSR Indirect Data Memory Address Pointer xxxx xxxx 30, 180
85h TRISA PORTA Data Direction Register 1111 1111 55, 181
86h TRISB PORTB Data Direction Register 1111 1111 64, 181
87h TRISC PORTC Data Direction Register 1111 1111 66, 181
88h
(5)
TRISD PORTD Data Direction Register 1111 1111 67, 181
89h
(5)
TRISE IBF
(5)
OBF
(5)
IBOV
(5)
PSPMODE
(5)
—
(8)
PORTE Data Direction bits 0000 1111 69, 181
8Ah
(1,4)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 23, 180
8Bh
(4)
INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 25, 180
8Ch PIE1 PSPIE
(3)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 24, 181
8Dh PIE2 OSFIE CMIE LVDIE —BCLIE— CCP3IE CCP2IE 000- 0-00 26, 181
8Eh PCON
— — — — — SBOREN POR BOR ---- -1qq 28, 181
8Fh OSCCON
— IRCF2 IRCF1 IRCF0 OSTS
(7)
IOFS SCS1 SCS0 -000 1000 38, 181
90h OSCTUNE
— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 36, 181
91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 105
92h PR2 Timer2 Period Register 1111 1111 86, 181
93h SSPADD Synchronous Serial Port (I
2
C™ mode) Address Register 0000 0000 101, 181
94h SSPSTAT SMP CKE D/A
PSR/WUA BF 0000 0000 101, 181
95h CCPR3L Capture/Compare/PWM Register 3 (LSB) xxxx xxxx 92
96h CCPR3H Capture/Compare/PWM Register 3 (MSB) xxxx xxxx 92
97h CCP3CON
— — CCP3X CCP3Y CCP3M3 CCP3M2 CCP3M1 CCP3M0 --00 0000 92
98h TXSTA CSRC TX9 TXEN SYNC
—BRGHTRMTTX9D0000 -010 145, 181
99h SPBRG Baud Rate Generator Register 0000 0000 145, 181
9Ah — Unimplemented — —
9Bh ADCON2
— — ACQT2 ACQT1 ACQT0 — — — --00 0--- 154
9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 55, 161
9Dh CVRCON CVREN CVROE CVRR
— CVR3 CVR2 CVR1 CVR0 000- 0000 55, 167
9Eh ADRESL A/D Result Register Low Byte xxxx xxxx 180
9Fh ADCON1 ADFM ADCS2 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 153, 181
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Details
on page
Legend: x = unknown, u = unchanged, q = value depends on condition, — = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> bits, whose contents
are transferred to the upper byte of the program counter during branches (CALL or GOTO).
2: Other (non Power-up) Resets include external Reset through MCLR
and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices (except for RE3), read as ‘0’.
6: This bit always reads as a ‘1’.
7: OSCCON<OSTS> bit resets to ‘0’ with dual-speed start-up and LP, HS or HS-PLL selected as the oscillator.
8: RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’.