Datasheet

 2003-2013 Microchip Technology Inc. DS30498D-page 181
PIC16F7X7
TRISA 1111 1111 1111 1111 uuuu uuuu
TRISB 1111 1111 1111 1111 uuuu uuuu
TRISC 1111 1111 1111 1111 uuuu uuuu
TRISD 1111 1111 1111 1111 uuuu uuuu
TRISE (PIC16F737/767)
TRISE (PIC16F747/777)
---- 1---
0000 1111
---- u---
0000 1111
---- 1---
uuuu uuuu
PIE1 0000 0000 0000 0000 -uuu uuuu
PIE2 000- 0-00 000- 0-00 uuu- u-uu
PCON ---- -1qq ---- -uuu ---- -uuu
OSCCON -000 1000 -000 1000 -uuu uuuu
OSCTUNE --00 0000 --00 0000 --uu uuuu
PR2 1111 1111 1111 1111 1111 1111
SSPADD 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 0000 0000 0000 0000 uuuu uuuu
TXSTA 0000 -010 0000 -010 uuuu -u1u
SPBRG 0000 0000 0000 0000 uuuu uuuu
CMCON 0000 0111 0000 0111 uuuu uuuu
CVRCON 000- 0000 000- 0000 uuu- uuuu
WDTCON ---0 1000 ---0 1000 ---u uuuu
ADRESL xxxx xxxx uuuu uuuu uuuu uuuu
ADCON1 0000 0000 0000 0000 uuuu uuuu
ADCON2 --00 0--- --00 0--- uuuu uuuu
PMDATA xxxx xxxx uuuu uuuu uuuu uuuu
PMADR xxxx xxxx uuuu uuuu uuuu uuuu
PMDATH --xx xxxx --uu uuuu --uu uuuu
PMADRH ---- xxxx ---- uuuu ---- uuuu
PMCON1 1--- ---0 1--- ---u 1--- ---u
LVDCON --00 0101 --00 0101 --uu uuuu
TABLE 15-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Power-on Reset,
Brown-out Reset
MCLR
Reset,
WDT Reset
Wake-up via WDT or
Interrupt
Legend: u = unchanged, x = unknown, — = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: One or more bits in INTCON, PIR1 and PR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 15-3 for Reset value for specific condition.