Datasheet

PIC16F7X7
DS30498D-page 106  2003-2013 Microchip Technology Inc.
10.4.2 OPERATION
The MSSP module functions are enabled by setting
MSSP enable bit, SSPEN (SSPCON<5>).
The SSPCON register allows control of the I
2
C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I
2
C modes to be selected:
•I
2
C Master mode, clock = Oscillator/4 (SSPADD + 1)
•I
2
C Slave mode (7-bit address)
•I
2
C Slave mode (10-bit address)
•I
2
C Slave mode (7-bit address), with Start and
Stop bit interrupts enabled
•I
2
C Slave mode (10-bit address), with Start and
Stop bit interrupts enabled
•I
2
C Firmware Controlled Master mode, slave is Idle
Selection of any I
2
C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits. To ensure proper operation
of the module, pull-up resistors must be provided
externally to the SCL and SDA pins.
10.4.3 SLAVE MODE
In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The MSSP module
will override the input state with the output data when
required (slave-transmitter).
To ensure proper communication of the I
2
C Slave
mode, the TRIS bits (TRISx [SDA, SCL]) correspond-
ing to the I
2
C pins must be set to ‘1’. If any TRIS bits
(TRISx<7:0>) of the port containing the I
2
C pins
(PORTx [SDA, SCL]) are changed in software, during
I
2
C communication using a Read-Modify-Write
instruction (BSF, BCF), then the I
2
C mode may stop
functioning properly and I
2
C communication may
suspend. Do not change any of the TRISx bits (TRIS
bits of the port containing the I
2
C pins) using the
instruction BSF or BCF during I
2
C communication. If it
is absolutely necessary to change the TRISx bits
during communication, the following method can be
used:
The I
2
C Slave mode hardware will always generate an
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
Start and Stop bits.
When an address is matched, or the data transfer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK
) pulse and
load the SSPBUF register with the received value
currently in the SSPSR register.
Any combination of the following conditions will cause
the MSSP module not to give this ACK
pulse:
• The Buffer Full bit, BF (SSPSTAT<0>), was set
before the transfer was received.
• The overflow bit, SSPOV (SSPCON<6>), was set
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The
BF bit is cleared by reading the SSPBUF register, while
bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I
2
C specification, as well as the requirement of the
MSSP module, are shown in timing parameter #100
and parameter #101.
10.4.3.1 Addressing
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPSR register. All incom-
ing bits are sampled with the rising edge of the clock
(SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
1. The SSPSR register value is loaded into the
SSPBUF register.
2. The Buffer Full bit, BF, is set.
3. An ACK
pulse is generated.
4. MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is
set (interrupt is generated if enabled) on the
falling edge of the ninth SCL pulse.
MOVF TRISC, W ; Example for a 40-pin part such as the PIC16F877A
IORLW 0x18 ; Ensures <4:3> bits are ‘11’
ANDLW B’11111001’ ; Sets <2:1> as output, but will not alter other bits
; User can use their own logic here, such as IORLW, XORLW and ANDLW
MOVWF TRISC