Datasheet
2004 Microchip Technology Inc. DS30498C-page 5
PIC16F7X7
1.0 DEVICE OVERVIEW
This document contains device specific information
about the following devices:
PIC16F737/767 devices are available only in 28-pin
packages, while PIC16F747/777 devices are available
in 40-pin and 44-pin packages. All devices in the
PIC16F7X7 family share common architecture with the
following differences:
• The PIC16F737 and PIC16F767 have one-half of
the total on-chip memory of the PIC16F747 and
PIC16F777.
• The 28-pin devices have 3 I/O ports, while the
40/44-pin devices have 5.
• The 28-pin devices have 16 interrupts, while the
40/44-pin devices have 17.
• The 28-pin devices have 11 A/D input channels,
while the 40/44-pin devices have 14.
• The Parallel Slave Port is implemented only on
the 40/44-pin devices.
• Low-Power modes: RC_RUN allows the core and
peripherals to be clocked from the INTRC, while
SEC_RUN allows the core and peripherals to be
clocked from the low-power Timer1. Refer to
Section 4.7 “Power-Managed Modes” for
further details.
• Internal RC oscillator with eight selectable
frequencies, including 31.25 kHz, 125 kHz,
250kHz, 500kHz, 1MHz, 2 MHz, 4 MHz and
8 MHz. The INTRC can be configured as a primary
or secondary clock source. Refer to Section 4.5
“Internal Oscillator Block” for further details.
• The Timer1 module current consumption has
been greatly reduced from 20 µA (previous PIC16
devices) to 1.8 µA typical (32 kHz at 2V), which is
ideal for real-time clock applications. Refer to
Section 7.0 “Timer1 Module” for further details.
• Extended Watchdog Timer (WDT) that can have a
programmable period from 1 ms to 268s. The WDT
has its own 16-bit prescaler. Refer to Section 15.17
“Watchdog Timer (WDT)” for further details.
• Two-Speed Start-up: When the oscillator is
configured for LP, XT or HS, this feature will clock
the device from the INTRC while the oscillator is
warming up. This, in turn, will enable almost
immediate code execution. Refer to
Section 15.17.3 “Two-Speed Clock Start-up
Mode” for further details.
• Fail-Safe Clock Monitor: This feature will allow the
device to continue operation if the primary or
secondary clock source fails by switching over to
the INTRC.
The available features are summarized in Table 1-1.
Block diagrams of the PIC16F737/767 and
PIC16F747/777 devices are provided in Figure 1-1 and
Figure 1-2, respectively. The pinouts for these device
families are listed in Table 1-2 and Table 1-3.
Additional information may be found in the “PICmicro
®
Mid-Range MCU Family Reference Manual”
(DS33023) which may be obtained from your local
Microchip Sales Representative or downloaded from
the Microchip web site. The Reference Manual should
be considered a complementary document to this data
sheet and is highly recommended reading for a better
understanding of the device architecture and operation
of the peripheral modules.
TABLE 1-1: PIC16F7X7 DEVICE FEATURES
• PIC16F737 • PIC16F767
• PIC16F747 • PIC16F777
Key Features PIC16F737 PIC16F747 PIC16F767 PIC16F777
Operating Frequency DC – 20 MHz DC – 20 MHz DC – 20 MHz DC – 20 MHz
Resets (and Delays) POR, BOR
(PWRT, OST)
POR, BOR
(PWRT, OST)
POR, BOR
(PWRT, OST)
POR, BOR
(PWRT, OST)
Flash Program Memory (14-bit words) 4K 4K 8K 8K
Data Memory (bytes) 368 368 368 368
Interrupts 16 17 16 17
I/O Ports Ports A, B, C Ports A, B, C, D, E Ports A, B, C Ports A, B, C, D, E
Timers 3333
Capture/Compare/PWM Modules 3 3 3 3
Master Serial Communications MSSP, AUSART MSSP, AUSART MSSP, AUSART MSSP, AUSART
Parallel Communications — PSP — PSP
10-bit Analog-to-Digital Module 11 Input Channels 14 Input Channels 11 Input Channels 14 Input Channels
Instruction Set 35 Instructions 35 Instructions 35 Instructions 35 Instructions
Packaging 28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
40-pin PDIP
44-pin QFN
44-pin TQFP
28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
40-pin PDIP
44-pin QFN
44-pin TQFP