Datasheet

 2004 Microchip Technology Inc. DS30498C-page 187
PIC16F7X7
REGISTER 15-4: WDTCON: WATCHDOG TIMER CONTROL REGISTER (ADDRESS 105h)
TABLE 15-6: SUMMARY OF WATCHDOG TIMER REGISTERS
U-0 U-0 U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0
— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN
bit 7 bit 0
bit 7-5 Unimplemented: Read as ‘0’
bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits
0000 = 1:32 Prescale rate
0001 = 1:64 Prescale rate
0010 = 1:128 Prescale rate
0011 = 1:256 Prescale rate
0100 = 1:512 Prescale rate
0101 = 1:1024 Prescale rate
0110 = 1:2048 Prescale rate
0111 = 1:4096 Prescale rate
1000 = 1:8192 Prescale rate
1001 = 1:16394 Prescale rate
1010 = 1:32768 Prescale rate
1011 = 1:65536 Prescale rate
1100 = 1:1 Prescale rate
bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit
(1)
1 = WDT is turned on
0 = WDT is turned off
Note 1: If WDTEN configuration bit = 1, then WDT is always enabled irrespective of this
control bit. If WDTEN configuration bit = 0, then it is possible to turn WDT on/off with
this control bit.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on
all other
Resets
81h, 181h OPTION_REG
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
2007h Configuration
bits
(1)
BORV0 BOREN MCLRE FOSC2 PWRTEN WDTEN FOSC1 FOSC0 1111 1111 1111 1111
105h WDTCON
— — — WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 15-1 for operation of these bits.