PIC16F7X7 Data Sheet 28/40/44-Pin, 8-Bit CMOS Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology 2004 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC16F7X7 28/40/44-Pin, 8-Bit CMOS Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology Low-Power Features: Peripheral Features: • Power-Managed modes: - Primary Run (XT, RC oscillator, 76 µA, 1 MHz, 2V) - RC_RUN (7 µA, 31.25 kHz, 2V) - SEC_RUN (9 µA, 32 kHz, 2V) - Sleep (0.1 µA, 2V) • Timer1 Oscillator (1.8 µA, 32 kHz, 2V) • Watchdog Timer (0.
PIC16F7X7 Pin Diagrams PDIP, SOIC, SSOP (28-pin) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7/PGD RB6/PGC RB5/AN13/CCP3 RB4/AN11 RB3/CCP2(1)/AN9 RB2/AN8 RB1/AN10 RB0/INT/AN12 VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RA1/AN1 RA0/AN0 MCLR/VPP/RE3 RB7/PGD RB6/PGC RB5/AN13/CCP3 RB4/AN11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC16F737/767 MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/LVDIN/SS/C2OUT VSS OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2(1) R
PIC16F7X7 Pin Diagrams (Continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7/PGD RB6/PGC RB5/AN13/CCP3 RB4/AN11 RB3/CCP2(1)/AN9 RB2/AN8 RB1/AN10 RB0/INT/AN12 VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2(1) NC MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4
PIC16F7X7 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Memory Organization ................................................................................................................................................................. 15 3.0 Reading Program Memory ...........................................................................
PIC16F7X7 1.0 DEVICE OVERVIEW This document contains device specific information about the following devices: • PIC16F737 • PIC16F747 • PIC16F767 • PIC16F777 PIC16F737/767 devices are available only in 28-pin packages, while PIC16F747/777 devices are available in 40-pin and 44-pin packages. All devices in the PIC16F7X7 family share common architecture with the following differences: • The PIC16F737 and PIC16F767 have one-half of the total on-chip memory of the PIC16F747 and PIC16F777.
PIC16F7X7 FIGURE 1-1: PIC16F737 AND PIC16F767 BLOCK DIAGRAM PORTA 13 Standard Flash Program Memory 4K/8K x 14 Program Bus Data Bus Program Counter RAM File Registers 368 x 8 8-Level Stack (13-bit) 14 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/LVDIN/ SS/C2OUT OSC2/CLKO/RA6 OSC1/CLKI/RA7 8 RAM Addr(1) PORTB 9 RB0/INT/AN12 RB1/AN10 RB2/AN8 RB3/CCP2(1)/AN9 RB4/AN11 RB5/AN13/CCP3 RB7/PGD:RB6/PGC Addr MUX Instruction Register Direct Addr 7 8 Indirect Addr FSR reg
PIC16F7X7 FIGURE 1-2: PIC16F747 AND PIC16F777 BLOCK DIAGRAM PORTA 13 Standard Flash Program Memory 4K/8K x 14 Program Bus RAM File Registers 368 x 8 8-Level Stack (13-bit) 14 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/LVDIN/ SS/C2OUT OSC2/CLKO/RA6 OSC1/CLKI/RA7 8 Data Bus Program Counter RAM Addr(1) PORTB 9 RB0/INT/AN12 RB1/AN10 RB2/AN8 RB3/CCP2(1)/AN9 RB4/AN11 RB5/AN13/CCP3 RB7/PGD:RB6/PGC Addr MUX Instruction Register Direct Addr 7 8 Indirect Addr FSR reg
PIC16F7X7 TABLE 1-2: PIC16F737 AND PIC16F767 PINOUT DESCRIPTION Pin Name OSC1/CLKI/RA7 OSC1 PDIP SOIC SSOP Pin # QFN Pin # 9 6 I/O/P Type I CLKI I RA7 I/O OSC2/CLKO/RA6 OSC2 10 7 — O RA6 I/O 1 26 ST ST I P I VPP RE3 Description ST/CMOS(3) Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; otherwise CMOS. External clock source input.
PIC16F7X7 TABLE 1-2: Pin Name PIC16F737 AND PIC16F767 PINOUT DESCRIPTION (CONTINUED) PDIP SOIC SSOP Pin # QFN Pin # I/O/P Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
PIC16F7X7 TABLE 1-2: PIC16F737 AND PIC16F767 PINOUT DESCRIPTION (CONTINUED) Pin Name PDIP SOIC SSOP Pin # QFN Pin # I/O/P Type Buffer Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI RC0 T1OSO T1CKI 11 RC1/T1OSI/CCP2 RC1 T1OSI CCP2(4) 12 RC2/CCP1 RC2 CCP1 13 RC3/SCK/SCL RC3 SCK SCL 14 RC4/SDI/SDA RC4 SDI SDA 15 RC5/SDO RC5 SDO 16 RC6/TX/CK RC6 TX CK 17 RC7/RX/DT RC7 RX DT 18 8 ST I/O O I 9 Digital I/O. Timer1 oscillator output. Timer1 external clock input.
PIC16F7X7 TABLE 1-3: PIC16F747 AND PIC16F777 PINOUT DESCRIPTION Pin Name OSC1/CLKI/RA7 OSC1 PDIP Pin # QFN Pin # TQFP Pin # 13 32 30 I/O/P Type I CLKI I RA7 I/O OSC2/CLKO/RA6 OSC2 14 33 31 — O RA6 I/O 1 18 18 ST ST I P I VPP RE3 Description ST/CMOS(4) Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; otherwise CMOS. External clock source input.
PIC16F7X7 TABLE 1-3: Pin Name PIC16F747 AND PIC16F777 PINOUT DESCRIPTION (CONTINUED) PDIP Pin # QFN Pin # TQFP Pin # I/O/P Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
PIC16F7X7 TABLE 1-3: PIC16F747 AND PIC16F777 PINOUT DESCRIPTION (CONTINUED) Pin Name PDIP Pin # QFN Pin # TQFP Pin # I/O/P Type Buffer Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI RC0 T1OSO T1CKI 15 RC1/T1OSI/CCP2 RC1 T1OSI CCP2(5) 16 RC2/CCP1 RC2 CCP1 17 RC3/SCK/SCL RC3 SCK 18 34 32 35 35 36 36 Digital I/O. Timer1 oscillator input. Capture 2 input, Compare 2 output, PWM 2 output. ST 37 37 Digital I/O. Capture 1 input, Compare 1 output, PWM 1 output.
PIC16F7X7 TABLE 1-3: Pin Name PIC16F747 AND PIC16F777 PINOUT DESCRIPTION (CONTINUED) PDIP Pin # QFN Pin # TQFP Pin # I/O/P Type Buffer Type Description PORTD is a bidirectional I/O port or Parallel Slave Port when interfacing to a microprocessor bus.
PIC16F7X7 2.0 MEMORY ORGANIZATION 2.2 Data Memory Organization The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 (Status<6>) and RP0 (Status<5>) are the bank select bits: There are two memory blocks in each of these PICmicro® MCUs. The program memory and data memory have separate buses so that concurrent access can occur and is detailed in this section.
PIC16F7X7 FIGURE 2-2: DATA MEMORY MAP FOR PIC16F737 AND THE PIC16F767 File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h File Address Indirect addr.
PIC16F7X7 FIGURE 2-3: DATA MEMORY MAP FOR PIC16F747 AND THE PIC16F777 File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h File Address Indirect addr.
PIC16F7X7 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in the peripheral feature section. The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device.
PIC16F7X7 TABLE 2-1: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on page Bank 1 80h(4) INDF 81h OPTION_REG 82h(4) PCL 83h(4) STATUS 84h(4) FSR Indirect Data Memory Address Pointer xxxx xxxx 30, 180 85h TRISA PORTA Data Direction Register 1111 1111 55, 181 Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 RBPU INTEDG T0CS T0SE PS2
PIC16F7X7 TABLE 2-1: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on page Bank 2 100h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 30, 180 101h TMR0 Timer0 Module Register 76, 180 102h(4) PCL Program Counter (PC) Least Significant Byte 103h(4) STATUS 104h(4) FSR 105h WDTCON 106h PORTB 107h — 108h — 109h IRP xxxx xxx
PIC16F7X7 2.2.2.1 Status Register The Status register contains the arithmetic status of the ALU, the Reset status and the bank select bits for data memory. The Status register can be the destination for any instruction, as with any other register. If the Status register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
PIC16F7X7 2.2.2.2 OPTION_REG Register Note: The OPTION_REG register is a readable and writable register which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register also known as the prescaler), the external INT interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 2-2: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer.
PIC16F7X7 2.2.2.3 INTCON Register Note: The INTCON register is a readable and writable register which contains various enable and flag bits for the TMR0 register overflow, RB port change and external RB0/INT pin interrupts. REGISTER 2-3: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>).
PIC16F7X7 2.2.2.4 PIE1 Register Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. The PIE1 register contains the individual enable bits for the peripheral interrupts.
PIC16F7X7 2.2.2.5 PIR1 Register The PIR1 register contains the individual flag bits for the peripheral interrupts. REGISTER 2-5: Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt bits are clear prior to enabling an interrupt.
PIC16F7X7 2.2.2.6 PIE2 Register The PIE2 register contains the individual enable bits for the CCP2 and CCP3 peripheral interrupts.
PIC16F7X7 2.2.2.7 PIR2 Register Note: The PIR2 register contains the flag bits for the CCP2 interrupt. REGISTER 2-7: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16F7X7 2.2.2.8 PCON Register Note: The Power Control (PCON) register contains flag bits to allow differentiation between a Power-on Reset (POR), a Brown-out Reset (BOR), a Watchdog Reset (WDT) and an external MCLR Reset. REGISTER 2-8: BOR is unknown on POR. It must be set by the user and checked on subsequent Resets to see if BOR is clear, indicating a brown-out has occurred.
PIC16F7X7 2.3 PCL and PCLATH The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register which is a readable and writable register. The upper bits (PC<12:8>) are not readable but are indirectly writable through the PCLATH register. On any Reset, the upper bits of the PC will be cleared. Figure 2-4 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH).
PIC16F7X7 2.5 EXAMPLE 2-2: Indirect Addressing, INDF and FSR Registers MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO CONTINUE : The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself indirectly (FSR = 0) will read 00h.
PIC16F7X7 3.0 READING PROGRAM MEMORY The Flash program memory is readable during normal operation over the entire VDD range. It is indirectly addressed through Special Function Registers (SFR). Up to 14-bit numbers can be stored in memory for use as calibration parameters, serial numbers, packed 7-bit ASCII, etc. Executing a program memory location containing data that forms an invalid instruction results in a NOP.
PIC16F7X7 3.3 Reading the Flash Program Memory 3.4 Flash program memory has its own code-protect mechanism. External read and write operations by programmers are disabled if this mechanism is enabled. A program memory location may be read by writing two bytes of the address to the PMADR and PMADRH registers and then setting control bit, RD (PMCON1<0>). Once the read control bit is set, the microcontroller will use the next two instruction cycles to read the data.
PIC16F7X7 4.0 OSCILLATOR CONFIGURATIONS 4.1 Oscillator Types TABLE 4-1: The PIC16F7X7 can be operated in eight different oscillator modes. The user can program three configuration bits (FOSC2:FOSC0) to select one of these eight modes (modes 5-8 are new PIC16 oscillator configurations): 1. 2. 3. 4.
PIC16F7X7 FIGURE 4-2: CERAMIC RESONATOR OPERATION (HS OR XT OSC CONFIGURATION) OSC1 C1 PIC16F7X7 (1) RES RF(3) Sleep OSC2 C2(1) RS(2) To Internal Logic 4.3 External Clock Input The ECIO Oscillator mode requires an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. In the ECIO Oscillator mode, the OSC2 pin becomes an additional general purpose I/O pin.
PIC16F7X7 4.4 RC Oscillator 4.5 For timing insensitive applications, the “RC” and “RCIO” device options offer additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal manufacturing variation.
PIC16F7X7 4.5.1 INTRC MODES 4.5.2 Using the internal oscillator as the clock source can eliminate the need for up to two external oscillator pins, after which it can be used for digital I/O. Two distinct configurations are available: • In INTIO1 mode, the OSC2 pin outputs FOSC/4, while OSC1 functions as RA7 for digital input and output. • In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6, both for digital input and output.
PIC16F7X7 4.6 Clock Sources and Oscillator Switching The PIC16F7X7 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low-frequency clock source. PIC16F7X7 devices offer three alternate clock sources. When enabled, these give additional options for switching to the various power-managed operating modes.
PIC16F7X7 4.6.3 CLOCK TRANSITION AND WDT When clock switching is performed, the Watchdog Timer is disabled because the Watchdog Ripple Counter is used as the Oscillator Start-up Timer (OST). Note: Once the clock transition is complete (i.e., new oscillator selection switch has occurred), the Watchdog Counter is re-enabled with the Counter Reset. This allows the user to synchronize the Watchdog Timer to the start of execution at the new clock frequency.
PIC16F7X7 FIGURE 4-6: PIC16F7X7 CLOCK DIAGRAM CONFIG1 (FOSC2:FOSC0) SCS<1:0> (T1OSC) Primary Oscillator OSC2 Sleep Secondary Oscillator T1OSC T1OSO To Timer1 T1OSCEN Enable Oscillator OSCCON<6:4> 8 MHz 4 MHz Internal Oscillator Block 8 MHz (INTOSC) 31.25 kHz (INTRC) 4.6.4 CPU 111 110 101 1 MHz 100 500 kHz 250 kHz 125 kHz 31.25 kHz MODIFYING THE IRCF BITS The IRCF bits can be modified at any time regardless of which clock source is currently being used as the system clock.
PIC16F7X7 4.6.5 CLOCK TRANSITION SEQUENCE • Clock before switch: One of INTOSC/INTOSC postscaler (IRCF<2:0> ≠ 000) 1. IRCF bits are modified to a different INTOSC/ INTOSC postscaler frequency. 2. The clock switching circuitry waits for a falling edge of the current clock, at which point CLKO is held low. 3. The clock switching circuitry then waits for eight falling edges of requested clock, after which it switches CLKO to this new clock source. 4. The IOFS bit is set. 5. Oscillator switchover is complete.
PIC16F7X7 4.7 Power-Managed Modes 4.7.1 If the system clock does not come from the INTRC (31.25 kHz) when the SCS bits are changed and the IRCF bits in the OSCCON register are configured for a frequency other than INTRC, the frequency may not be stable immediately. The IOFS bit (OSCCON<2>) will be set when the INTOSC or postscaler frequency is stable, after 4 ms (approx.).
PIC16F7X7 4.7.2 SEC_RUN MODE The core and peripherals can be configured to be clocked by T1OSC using a 32.768 kHz crystal. The crystal must be connected to the T1OSO and T1OSI pins. This is the same configuration as the low-power timer circuit (see Section 7.6 “Timer1 Oscillator”). When SCS bits are configured to run from T1OSC, a clock transition is generated.
PIC16F7X7 4.7.3 SEC_RUN/RC_RUN TO PRIMARY CLOCK SOURCE When switching from a SEC_RUN or RC_RUN mode back to the primary system clock, following a change of SCS<1:0> to ‘00’, the sequence of events that take place will depend upon the value of the FOSC bits in the Configuration register. If the primary clock source is configured as a crystal (HS, XT or LP), then the transition will take place after 1024 clock cycles.
PIC16F7X7 FIGURE 4-9: TIMING FOR TRANSITION BETWEEN SEC_RUN/RC_RUN AND PRIMARY CLOCK Q4 Q1 Q2 Q3 Q4 TT1P(1) or TINP(2) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Secondary Oscillator OSC1 TOST(6) OSC2 TOSC(3) Primary Clock TSCS(4) System Clock TDLY(5) SCS<1:0> OSTS Program Counter Note 1: 2: 3: 4: 5: 6: PC PC + 1 PC + 2 PC + 3 TT1P = 30.52 µs. TINP = 32 µs typical. TOSC = 50 ns minimum. TSCS = 8 TINP OR 8 TT1P. TDLY = 1 TINP OR 1 TT1P. Refer to parameter D032 in Section 18.0 “Electrical Characteristics”.
PIC16F7X7 4.7.3.2 Returning to Primary Oscillator with a Reset A Reset will clear SCS<1:0> back to ‘00’. The sequence for starting the primary oscillator following a Reset is the same for all forms of Reset, including POR. There is no transition sequence from the alternate system clock to the primary system clock on a Reset condition. Instead, the device will reset the state of the OSCCON register and default to the primary system clock.
PIC16F7X7 FIGURE 4-11: TIMING LP CLOCK TO PRIMARY SYSTEM CLOCK AFTER RESET (EC, RC, INTRC) TT1P(1) Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 T1OSI OSC1 OSC2 TCPU(2) CPU Start-up System Clock MCLR OSTS Program Counter Note 1: 2: PC 0000h 0001h 0002h 0003h 0004h TT1P = 30.52 µs. TCPU = 5-10 µs. DS30498C-page 46 2004 Microchip Technology Inc.
PIC16F7X7 TABLE 4-4: Current System Clock CLOCK SWITCHING MODES SCS bits<1:0> Modified to: Delay OSTS bit IOFS T1RUN bit bit New System Clock LP, XT, HS, 10 T1OSC, (INTRC) EC, RC FOSC<2:0> = LP, XT or HS 8 Clocks of INTRC 0 1(1) 0 LP, XT, HS, 01 INTRC, (T1OSC) EC, RC FOSC<2:0> = LP, XT or HS 8 Clocks of T1OSC 0 N/A 1 T1OSC EC or RC Comments INTRC The internal RC oscillator or frequency is dependant upon INTOSC the IRCF bits. or INTOSC Postscaler T1OSCEN bit must be enabled.
PIC16F7X7 4.7.4 EXITING SLEEP WITH AN INTERRUPT Any interrupt, such as WDT or INT0, will cause the part to leave the Sleep mode. The SCS bits are unaffected by a SLEEP command and are the same before and after entering and leaving Sleep. The clock source used after an exit from Sleep is determined by the SCS bits. 4.7.4.1 Sequence of Events If SCS<1:0> = 00: 1. 2. 3. The device is held in Sleep until the CPU start-up time-out is complete.
PIC16F7X7 5.0 I/O PORTS Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the “PICmicro® Mid-Range MCU Family Reference Manual” (DS33023). 5.1 PORTA and the TRISA Register PORTA is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISA.
PIC16F7X7 FIGURE 5-1: BLOCK DIAGRAM OF RA0/AN0:RA1/AN1 PINS FIGURE 5-2: Data Bus Data Bus D Q CK Q D P WR TRISA Q D Q N CK CK Q VSS TRIS Latch P Data Latch Data Latch D Q VDD WR PORTA VDD WR PORTA BLOCK DIAGRAM OF RA3/AN3/VREF+ PIN I/O pin WR TRISA Q N CK Q VSS TRIS Latch Analog Input Mode Analog Input Mode TTL Input Buffer RD TRISA Q Q To A/D Module Channel Input D EN EN To Comparator TTL Input Buffer RD TRISA D RD PORTA I/O pin RD PORTA To Comparator To A/D Modul
PIC16F7X7 FIGURE 5-3: BLOCK DIAGRAM OF RA2/AN2/VREF-/CVREF PIN Data Bus Q D VDD WR PORTA CK Q P Data Latch D Q RA2/AN2/VREF-/ CVREF pin N WR TRISA CK Q VSS TRIS Latch Analog Input Mode TTL Input Buffer RD TRISA Q D EN RD PORTA To Comparator To A/D Module VREFTo A/D Module Channel Input CVROE CVREF FIGURE 5-4: Data Bus BLOCK DIAGRAM OF RA4/T0CKI/C1OUT PIN Comparator Mode = 011, 101, 001 D WR PORTA Q Comparator 1 Output 1 CK Q Data Latch D WR TRISA 0 Q N CK RA4/T0CKI/ C1OUT pin
PIC16F7X7 FIGURE 5-5: Data Bus BLOCK DIAGRAM OF RA5/AN4/LVDIN/SS/C2OUT PIN Comparator Mode = 011, 101 D Q Comparator 2 Output WR PORTA CK Q Data Latch D VDD 1 P 0 Q N WR TRISA CK RA5/AN4/LVDIN/ SS/C2OUT pin Q TRIS Latch Analog Input Mode VSS TTL Buffer RD TRISA Q D EN RD PORTA SS Input LVDIN To A/D Module Channel Input DS30498C-page 52 2004 Microchip Technology Inc.
PIC16F7X7 FIGURE 5-6: BLOCK DIAGRAM OF OSC2/CLKO/RA6 PIN (FOSC = 1x1) From OSC1 CLKO (FOSC/4) 1 Oscillator Circuit 0 VDD Data Bus OSC2/CLKO D WR PORTA CK Q VDD Q P Data Latch D WR TRISA Q N CK Q (FOSC = 1x1) TRIS Latch EMUL VSS EMUL + FOSC = 00x,010 (FOSC = 1x0,011) RD TRISA Q EMUL D TTL Buffer 1 EN 0 RD PORTA RA6 pin (FOSC = 1x0,011) VDD P N (FOSC = 1x1) EMUL + FOSC = 00x, 010 VSS Note 1: CLKO signal is 1/4 of the FOSC frequency. 2004 Microchip Technology Inc.
PIC16F7X7 FIGURE 5-7: BLOCK DIAGRAM OF OSC1/CLKI/RA7 PIN Oscillator Circuit VDD (FOSC = 011) Data Bus D WR PORTA Q CK OSC1/CLKI VDD Q P Data Latch Q D WR TRISA N CK Q TRIS Latch (FOSC = 10x) + EMUL VSS (FOSC = 10x) RD TRISA Q D NEMUL 1 EN TTL Buffer 0 RD PORTA RA7 pin (FOSC = 10x) VDD P N (FOSC = 10x) + EMUL VSS DS30498C-page 54 2004 Microchip Technology Inc.
PIC16F7X7 TABLE 5-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 bit 0 TTL Input/output or analog input. RA1/AN1 bit 1 TTL Input/output or analog input. RA2/AN2/VREF-/CVREF bit 2 TTL Input/output or analog input or VREF-. RA3/AN3/VREF+ bit 3 TTL Input/output or analog input or VREF+. RA4/T0CKI/C1OUT bit 4 ST Input/output or external clock input for Timer0. Output is open-drain type.
PIC16F7X7 5.2 PORTB and the TRISB Register PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). Each of the PORTB pins has a weak internal pull-up.
PIC16F7X7 FIGURE 5-8: BLOCK DIAGRAM OF RB0/INT/AN12 PIN VDD Analog Input Mode RBPU (1) Data Bus WR PORTB Weak P Pull-up Data Latch D Q I/O pin CK TRIS Latch D Q WR TRISB Analog Input Mode CK TTL Input Buffer RD TRISB D Q RD PORTB EN Analog Input Mode RD PORTB To INT To A/D Channel Input Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
PIC16F7X7 FIGURE 5-10: BLOCK DIAGRAM OF RB2/AN8 PIN VDD RBPU(1) Data Bus WR PORTB Weak P Pull-up Data Latch D Q I/O pin CK TRIS Latch D Q WR TRISB CK Analog Input Mode TTL Input Buffer RD TRISB Q RD PORTB D EN RD PORTB To A/D Channel Input Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. DS30498C-page 58 2004 Microchip Technology Inc.
PIC16F7X7 FIGURE 5-11: BLOCK DIAGRAM OF RB3/CCP2(1)/AN9 PIN Analog Input Mode CCP2 Output Select and CCPMX CCP2 Output 1 0 VDD RBPU(2) Data Bus WR PORTB Weak P Pull-up VDD Data Latch D Q P CK N I/O pin VSS TRIS Latch D Q WR TRISB CK Q Analog Input Mode TTL Input Buffer RD TRISB Q RD PORTB D EN RD PORTB To A/D Channel Input Schmitt Trigger Buffer(3) Analog Input Mode To CCP Module Input Note 1: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.
PIC16F7X7 FIGURE 5-12: BLOCK DIAGRAM OF RB4/AN11 PIN Analog Input Mode RBPU(1) VDD Weak P Pull-up VDD P Data Latch Data Bus WR PORTB D Q TRIS Latch D Q WR TRISB I/O pin N CK VSS CK RD TRISB Analog Input Mode TTL Input Buffer Latch Q D RD PORTB Set RBIF From other RB7:RB4 pins EN Q1 Analog Input Mode Q D EN RD PORTB Q3 To A/D channel input Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. DS30498C-page 60 2004 Microchip Technology Inc.
PIC16F7X7 FIGURE 5-13: BLOCK DIAGRAM OF RB5/AN13/CCP3 PIN Analog Input Mode CCP3 Output Select CCP3 Output 1 0 VDD RBPU(1) Weak P Pull-up Data Latch D Q Data Bus I/O pin WR PORTB CK TRIS Latch D Q WR TRISB CK Analog Input Mode TTL Input Buffer RD TRISB Latch Q D RD PORTB Set RBIF Q From other RB7:RB4 pins To CCP Module Input EN Q1 Analog Input Mode Schmitt Trigger Buffer Analog Input Mode D EN RD PORTB Q3 To A/D Channel Input Note 1: To enable weak pull-ups, set the appropriate TRIS
PIC16F7X7 FIGURE 5-14: BLOCK DIAGRAM OF RB6/PGC PIN Program Mode/ICD VDD RBPU(1) Weak P Pull-up Data Latch D Q Data Bus I/O pin WR PORTB CK TRIS Latch D Q WR TRISB CK TTL Input Buffer RD TRISB Latch Q D Set RBIF RD PORTB EN Program Mode/ICD Q From other RB7:RB4 pins D RD PORTB EN PGC Q1 Schmitt Trigger Buffer Q3 Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. DS30498C-page 62 2004 Microchip Technology Inc.
PIC16F7X7 FIGURE 5-15: BLOCK DIAGRAM OF RB7/PGD PIN Port/Program Mode/ICD PGD 1 0 VDD RBPU(1) Weak P Pull-up Data Latch D Q Data Bus I/O pin WR PORTB CK TRIS Latch D Q WR TRISB 0 CK 1 TTL Input Buffer RD TRISB PGD DRVEN Latch Q D RD PORTB Set RBIF From other RB7:RB4 pins EN Program Mode/ICD Q D EN Q1 RD PORTB Q3 PGD Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 2004 Microchip Technology Inc.
PIC16F7X7 TABLE 5-3: PORTB FUNCTIONS Name Bit# Buffer Function RB0/INT/AN12 bit 0 RB1/AN10 bit 1 TTL Input/output pin. Internal software programmable weak pull-up or analog input. RB2/AN8 bit 2 TTL Input/output pin. Internal software programmable weak pull-up or analog input. RB3/CCP2/AN9 bit 3 TTL Input/output pin or Capture 2 input/Compare 2 output/PWM 2 output. Internal software programmable weak pull-up or analog input.
PIC16F7X7 5.3 PORTC and the TRISC Register PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). PORTC is multiplexed with several peripheral functions (Table 5-5).
PIC16F7X7 TABLE 5-5: PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit 0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input. RC1/T1OSI/CCP2 bit 1 ST Input/output port pin or Timer1 oscillator input or Capture 2 input/ Compare 2 output/PWM 2 output. RC2/CCP1 bit 2 ST Input/output port pin or Capture 1 input/Compare 1 output/PWM 1 output. RC3/SCK/SCL bit 3 ST RC3 can also be the synchronous serial clock for both SPI™ and I2C™ modes.
PIC16F7X7 5.4 FIGURE 5-18: PORTD and TRISD Registers This section is not applicable to the PIC16F737 or PIC16F767. Data Bus PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configureable as an input or output. PORTD BLOCK DIAGRAM (IN I/O PORT MODE) D Q I/O pin(1) WR Port CK Data Latch PORTD can be configured as an 8-bit wide microprocessor port (Parallel Slave Port) by setting control bit, PSPMODE (TRISE<4>). In this mode, the input buffers are TTL.
PIC16F7X7 5.5 FIGURE 5-19: PORTE and TRISE Register This section is not applicable to the PIC16F737 or PIC16F767. PORTE has four pins, RE0/RD/AN5, RE1/WR/AN6, RE2/CS/AN7 and MCLR/VPP/RE3, which are individually configureable as inputs or outputs. These pins have Schmitt Trigger input buffers. RE3 is only available as an input if MCLRE is ‘0’ in Configuration Word 1.
PIC16F7X7 REGISTER 5-1: TRISE REGISTER (ADDRESS 89h) R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE —(1) TRISE2 TRISE1 TRISE0 bit 7 bit 0 bit 7 Parallel Slave Port Status/Control bits: IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Bu
PIC16F7X7 5.6 Parallel Slave Port The Parallel Slave Port (PSP) is not implemented on the PIC16F737 or PIC16F767. PORTD operates as an 8-bit wide Parallel Slave Port or microprocessor port when control bit, PSPMODE (TRISE<4>), is set. In Slave mode, it is asynchronously readable and writable by an external system using the read control input pin RE0/RD/AN5, the write control input pin RE1/WR/AN6 and the chip select control input pin RE2/CS/AN7.
PIC16F7X7 FIGURE 5-21: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 5-22: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 5-11: Address 08h REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name PORTD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 1 Bit 0 Port Data Latch when written: Port pins when read 09h PORTE — — — — RE3 89h TRISE IBF OBF IB
PIC16F7X7 NOTES: DS30498C-page 72 2004 Microchip Technology Inc.
PIC16F7X7 6.0 TIMER0 MODULE Counter mode is selected by setting bit, T0CS (OPTION_REG<5>). In Counter mode, Timer0 will increment, either on every rising or falling edge of pin RA4/T0CKI/C1OUT. The incrementing edge is determined by the Timer0 Source Edge Select bit, T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.3 “Using Timer0 With an External Clock”.
PIC16F7X7 6.3 Using Timer0 With an External Clock When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2 TOSC (and a small RC delay of 20 ns) and low for at least 2 TOSC (and a small RC delay of 20 ns).
PIC16F7X7 REGISTER 6-1: OPTION_REG: OPTION CONTROL REGISTER (ADDRESS 181h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA(1) PS2 PS1 PS0 bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal i
PIC16F7X7 EXAMPLE 6-1: CLRWDT BANKSEL MOVLW MOVWF CHANGING THE PRESCALER ASSIGNMENT FROM WDT TO TIMER0 TABLE 6-1: Name 01h,101h TMR0 0Bh,8Bh, 10Bh,18Bh INTCON Legend: Clear WDT and prescaler Select Bank of OPTION_REG Select TMR0, new prescale value and clock source REGISTERS ASSOCIATED WITH TIMER0 Address 81h,181h ; ; ; ; OPTION_REG b'xxxx0xxx' OPTION_REG OPTION_REG Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Timer0 Module Register GIE PEIE RBPU INTEDG Value on all other Rese
PIC16F7X7 7.0 TIMER1 MODULE The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L) which are readable and writable. The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit, TMR1IE (PIE1<0>).
PIC16F7X7 REGISTER 7-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h) U-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 T1RUN: Timer1 System Clock Status bit 1 = System clock is derived from Timer1 oscillator 0 = System clock is derived from another source bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 0
PIC16F7X7 7.2 Timer1 Operation in Timer Mode 7.4 Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is FOSC/4. The synchronize control bit, T1SYNC (T1CON<2>), has no effect since the internal clock is always in sync. 7.3 Counter mode is selected by setting bit TMR1CS. In this mode, the timer increments on every rising edge of clock input on pin RC1/T1OSI/CCP2 when bit T1OSCEN is set, or on pin RC0/T1OSO/T1CKI when bit T1OSCEN is cleared.
PIC16F7X7 7.5 Timer1 Operation in Asynchronous Counter Mode If control bit, T1SYNC (T1CON<2>), is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt on overflow that will wake-up the processor. However, special precautions in software are needed to read/write the timer (Section 7.5.1 “Reading and Writing Timer1 in Asynchronous Counter Mode”).
PIC16F7X7 7.6 Timer1 Oscillator 7.7 A crystal oscillator circuit is built between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit, T1OSCEN (T1CON<3>). The oscillator is a low-power oscillator, rated up to 32.768 kHz. It will continue to run during all power-managed modes. It is primarily intended for a 32 kHz crystal. The circuit for a typical LP oscillator is shown in Figure 7-3. Table 7-1 shows the capacitor selection for the Timer1 oscillator.
PIC16F7X7 7.9 Resetting Timer1 Register Pair (TMR1H, TMR1L) battery or supercapacitor as a power source, it can completely eliminate the need for a separate RTC device and battery backup. TMR1H and TMR1L registers are not reset to 00h on a POR, or any other Reset, except by the CCP1 special event triggers. T1CON register is reset to 00h on a Power-on Reset or a Brown-out Reset, which shuts off the timer and leaves a 1:1 prescale. In all other Resets, the register is unaffected. 7.
PIC16F7X7 TABLE 7-2: Address REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Name 0Bh, 8Bh, INTCON 10Bh, 18Bh Value on all other Resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0Eh TMR1L Holding Register for the
PIC16F7X7 NOTES: DS30498C-page 84 2004 Microchip Technology Inc.
PIC16F7X7 8.0 TIMER2 MODULE Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time base for the PWM mode of the CCP module(s). The TMR2 register is readable and writable and is cleared on any device Reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits, T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer2 module has an 8-bit period register, PR2.
PIC16F7X7 REGISTER 8-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h) U-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale 0010 = 1:3 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 0
PIC16F7X7 9.0 CAPTURE/COMPARE/PWM MODULES Each Capture/Compare/PWM (CCP) module contains a 16-bit register which can operate as a: • 16-bit Capture register • 16-bit Compare register • PWM Master/Slave Duty Cycle register The CCP1, CCP2 and CCP3 modules are identical in operation, with the exception being the operation of the special event trigger. Table 9-1 and Table 9-2 show the resources and interactions of the CCP module(s).
PIC16F7X7 REGISTER 9-1: CCPxCON: CCPx CONTROL REGISTER (ADDRESS 17h, 1Dh, 97h) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 CCPxX:CCPxY: PWM Least Significant bits Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
PIC16F7X7 9.4 Capture Mode 9.4.4 In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as one of the following and is configured by CCPxCON<3:0>: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge An event is selected by control bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit, CCP1IF (PIR1<2>), is set.
PIC16F7X7 9.5.1 CCP PIN CONFIGURATION 9.5.4 The user must configure the RC2/CCP1 pin as an output by clearing the TRISC<2> bit. Note: 9.5.2 In this mode, an internal hardware trigger is generated which may be used to initiate an action. Clearing the CCP1CON register will force the RC2/CCP1 compare output latch to the default low level. This is not the PORTC I/O data latch. The special event trigger output of CCP1 resets the TMR1 register pair.
PIC16F7X7 9.6 9.6.1 PWM Mode (PWM) In Pulse-Width Modulation mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. PWM PERIOD The PWM period is specified by writing to the PR2 register.
PIC16F7X7 The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the formula: 9.6.3 The following steps should be taken when configuring the CCP module for PWM operation: 1. 2.
PIC16F7X7 10.0 10.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE FIGURE 10-1: Internal Data Bus Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC16F7X7 10.3.1 REGISTERS The MSSP module has four registers for SPI mode operation. These are: • • • • In receive operations, SSPSR and SSPBUF together create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set.
PIC16F7X7 REGISTER 10-2: SSPCON: MSSP CONTROL (SPI MODE) REGISTER 1 (ADDRESS 14h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitting the previous word. (Must be cleared in software.
PIC16F7X7 10.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON<5:0> and SSPSTAT<7:6>).
PIC16F7X7 10.3.3 ENABLING SPI I/O 10.3.4 To enable the serial port, SSP Enable bit, SSPEN (SSPCON<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed.
PIC16F7X7 10.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 10-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input).
PIC16F7X7 10.3.6 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times, as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data.
PIC16F7X7 FIGURE 10-5: SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle after Q2↓ SSPSR to SSPBUF FIGURE 10-6: SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) bit 6 bit 7 bit 7 bit 5 bit 4 bit
PIC16F7X7 10.3.8 SLEEP OPERATION 10.3.10 In Master mode, all module clocks are halted and the transmission/reception will remain in that state until the device wakes from Sleep. After the device returns to normal mode, the module will continue to transmit/ receive data. Table 10-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits. TABLE 10-1: In Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device.
PIC16F7X7 10.4 I2C Mode 10.4.1 The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing.
PIC16F7X7 REGISTER 10-3: SSPSTAT: MSSP STATUS (I2C MODE) REGISTER (ADDRESS 94h) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs bit 5 D/A: Data/Addre
PIC16F7X7 REGISTER 10-4: SSPCON: MSSP CONTROL (I2C MODE) REGISTER 1 (ADDRESS 14h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPBUF register is written while it is s
PIC16F7X7 REGISTER 10-5: SSPCON2: MSSP CONTROL (I2C MODE) REGISTER 2 (ADDRESS 91h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was rece
PIC16F7X7 10.4.2 OPERATION 10.4.3 The MSSP module functions are enabled by setting MSSP enable bit, SSPEN (SSPCON<5>). The SSPCON register allows control of the I2C operation.
PIC16F7X7 In 10-bit Address mode, two address bytes need to be received by the slave. The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs of the address.
DS30498C-page 108 CKP 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 (CKP does not reset to ‘0’ when SEN = 0) SSPOV (SSPCON<6>) BF (SSPSTAT<0>) SSPIF (PIR1<3>) 1 SCL S A7 7 A1 8 9 ACK R/W = 0 1 D7 3 4 D4 5 D3 Receiving Data D5 Cleared in software SSPBUF is read 2 D6 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 4 D4 5 D3 Receiving Data D5 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPBUF is still full. ACK is not sent.
2004 Microchip Technology Inc.
DS30498C-page 110 2 1 4 1 5 0 7 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 6 A9 A8 8 9 (CKP does not reset to ‘0’ when SEN = 0) UA (SSPSTAT<1>) SSPOV (SSPCON<6>) CKP 3 1 Cleared in software BF (SSPSTAT<0>) SSPIF (PIR1<3>) 1 SCL S 1 ACK R/W = 0 A7 2 4 A4 5 A3 6 A2 8 9 A0 ACK UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address 7 A1 Cleared in so
2004 Microchip Technology Inc. 2 CKP (SSPCON<4>) UA (SSPSTAT<1>) BF (SSPSTAT<0>) SSPIF (PIR1<3>) 1 S SCL 1 4 1 5 0 6 7 A9 A8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 3 1 Receive First Byte of Address 1 8 9 ACK 1 3 4 5 Cleared in software 2 7 UA is set indicating that SSPADD needs to be updated 8 A1 A0 Cleared by hardware when SSPADD is updated with low byte of address.
PIC16F7X7 10.4.4 CLOCK STRETCHING Both 7-bit and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence. 10.4.4.
PIC16F7X7 10.4.4.5 Clock Synchronization and the CKP Bit When the CKP bit is cleared, the SCL output is forced to ‘0’; however, setting the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL.
DS30498C-page 114 CKP SSPOV (SSPCON<6>) BF (SSPSTAT<0>) SSPIF (PIR1<3>) 1 SCL S A7 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 7 A1 8 9 ACK R/W = 0 3 4 D4 5 D3 Receiving Data D5 Cleared in software 2 D6 If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to ‘0’ and no clock stretching will occur SSPBUF is read 1 D7 6 D2 7 D1 9 ACK 1 D7 BF is set after falling edge of the 9th clock, CKP is reset to ‘0’ and clock stretching occurs 8
2004 Microchip Technology Inc. 2 1 UA (SSPSTAT<1>) SSPOV (SSPCON<6>) CKP 3 1 4 1 5 0 6 A9 7 A8 8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR Cleared in software BF (SSPSTAT<0>) SSPIF (PIR1<3>) 1 SCL S 1 9 ACK R/W = 0 A7 2 4 A4 5 A3 6 A2 Cleared in software 3 A5 7 A1 8 Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set.
PIC16F7X7 10.4.5 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices.
PIC16F7X7 MASTER MODE Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled.
PIC16F7X7 10.4.6.1 I2C Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA while SCL outputs the serial clock.
PIC16F7X7 10.4.7 BAUD RATE GENERATOR Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state. 2 In I C Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPADD register (Figure 10-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting.
PIC16F7X7 10.4.7.1 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and begins counting.
PIC16F7X7 10.4.8 I2C MASTER MODE START CONDITION TIMING 10.4.8.1 If the user writes the SSPBUF when a Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). To initiate a Start condition, the user sets the Start Condition Enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and starts its count.
PIC16F7X7 10.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING Immediately following the SSPIF bit getting set, the user may write the SSPBUF with the 7-bit address in 7-bit mode or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode).
PIC16F7X7 10.4.10 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address, is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full flag bit, BF and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification parameter #106).
DS30498C-page 124 S R/W PEN SEN BF (SSPSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared in software 2 6 7 8 After Start condition, SEN cleared by hardware SSPBUF written 1 9 D7 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPBUF is written in software Cleared in software service routine from SSP interrupt 2 D6 P Cleared in software 9 Transmitting Data or Second Half of 10-bit Address ACK 1 SCL held low while CPU responds to SSPIF ACK = 0 R/W = 0 SSPBUF written with 7-
2004 Microchip Technology Inc.
PIC16F7X7 10.4.12 ACKNOWLEDGE SEQUENCE TIMING 10.4.13 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPCON2<2>). At the end of a receive/ transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’.
PIC16F7X7 10.4.14 SLEEP OPERATION 10.4.17 2 While in Sleep mode, the I C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 10.4.15 EFFECT OF A RESET A Reset disables the MSSP module and terminates the current transfer. 10.4.
PIC16F7X7 10.4.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 10-26). SCL is sampled low before SDA is asserted low (Figure 10-27). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 10-28).
PIC16F7X7 FIGURE 10-27: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF.
PIC16F7X7 10.4.17.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, see Figure 10-29). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from highto-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time.
PIC16F7X7 10.4.17.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 10-31).
PIC16F7X7 NOTES: DS30498C-page 132 2004 Microchip Technology Inc.
PIC16F7X7 11.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (AUSART) The AUSART can be configured in the following modes: • Asynchronous (full-duplex) • Synchronous – Master (half-duplex) • Synchronous – Slave (half-duplex) The Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) module is one of the two serial I/O modules. (AUSART is also known as a Serial Communications Interface or SCI.
PIC16F7X7 REGISTER 11-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins) 0 = Serial port disabled bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care.
PIC16F7X7 11.1 AUSART Baud Rate Generator (BRG) It may be advantageous to use the high baud rate (BRGH = 1) even for slower baud clocks. This is because the FOSC/(16(X + 1)) equation can reduce the baud rate error in some cases. The BRG supports both the Asynchronous and Synchronous modes of the AUSART. It is a dedicated 8-bit Baud Rate Generator. The SPBRG register controls the period of a free running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTA<2>) also controls the baud rate.
PIC16F7X7 TABLE 11-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) FOSC = 20 MHz Baud Rate (K) Kbaud % Error FOSC = 16 MHz SPBRG Value (decimal) Kbaud % Error FOSC = 10 MHz SPBRG Value (decimal) Kbaud % Error SPBRG Value (decimal) 0.3 — — — — — — — — — 1.2 1.221 1.75 255 1.202 0.17 207 1.202 0.17 129 2.4 2.404 0.17 129 2.404 0.17 103 2.404 0.17 64 9.6 9.766 1.73 31 9.615 0.16 25 9.766 1.73 15 19.2 19.531 1.72 15 19.231 0.16 12 19.531 1.72 7 28.
PIC16F7X7 TABLE 11-5: INTRC BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) FOSC = 8 MHz Baud Rate (K) Kbaud % Error FOSC = 4 MHz SPBRG Value (decimal) Kbaud FOSC = 2 MHz % Error SPBRG Value (decimal) Kbaud FOSC = 1 MHz % Error SPBRG Value (decimal) Kbaud % Error SPBRG Value (decimal) 0.3 NA — — 0.300 0 207 0.300 0 103 0.300 0 51 1.2 1.202 +0.16 103 1.202 +0.16 51 1.202 +0.16 25 1.202 +0.16 12 2.4 2.404 +0.16 51 2.404 +0.16 25 2.404 +0.16 12 2.232 -6.
PIC16F7X7 11.2 AUSART Asynchronous Mode interrupt can be enabled/disabled by setting/clearing enable bit, TXIE (PIE1<4>). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. Status bit TRMT is a read-only bit which is set when the TSR register is empty.
PIC16F7X7 When setting up an Asynchronous Transmission, follow these steps: 5. 1. 6. Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is desired, set bit BRGH (see Section 11.1 “AUSART Baud Rate Generator (BRG)”). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set transmit bit TX9. 2. 3. 4.
PIC16F7X7 11.2.2 AUSART ASYNCHRONOUS RECEIVER is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting to the RSR register. On the detection of the Stop bit of the third byte, if the RCREG register is still full, the Overrun Error bit, OERR (RCSTA<1>), will be set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Overrun bit, OERR, has to be cleared in software.
PIC16F7X7 When setting up an Asynchronous Reception, follow these steps: 1. 2. 3. 4. 5. 6. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE is set. 7. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREG register. 9. If any error occurred, clear the error by clearing enable bit CREN. 10.
PIC16F7X7 11.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT • Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. • Read the RCSTA register to get the ninth bit and determine if any error occurred during reception. • Read the 8-bit received data by reading the RCREG register to determine if the device is being addressed. • If any error occurred, clear the error by clearing enable bit CREN.
PIC16F7X7 FIGURE 11-7: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT Start bit RC7/RX/DT (pin) bit 0 bit 1 bit 8 Stop bit Start bit bit 0 bit 8 Stop bit Load RSR bit 8 = 0, Data Byte bit 8 = 1, Address Byte Word 1 RCREG Read RCIF Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer) because ADDEN = 1.
PIC16F7X7 11.3 AUSART Synchronous Master Mode In Synchronous Master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit, SYNC (TXSTA<4>). In addition, enable bit, SPEN (RCSTA<7>), is set in order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and DT (data) lines, respectively.
PIC16F7X7 TABLE 11-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Address Name Bit 7 Bit 6 0Bh, 8Bh, INTCO 10Bh,18Bh N GIE PEIE PSPIF(1) ADIF RCIF SPEN RX9 SREN 0Ch PIR1 18h RCSTA 19h TXREG PSPIE PIE1 98h TXSTA 99h SPBRG Legend: Note 1: Bit 4 TMR0IE INT0IE TXIF Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u SSPIF CCP1IF TMR2IF FERR OERR CREN ADDEN TMR1IF 0000 0000 RX9D ADIE RCIE
PIC16F7X7 11.3.2 AUSART SYNCHRONOUS MASTER RECEPTION data. Reading the RCREG register will load bit RX9D with a new value; therefore, it is essential for the user to read the RCSTA register before reading RCREG in order not to lose the old RX9D information. Once Synchronous mode is selected, reception is enabled by setting either enable bit, SREN (RCSTA<5>) or enable bit, CREN (RCSTA<4>). Data is sampled on the RC7/RX/DT pin on the falling edge of the clock.
PIC16F7X7 FIGURE 11-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 RC6/TX/CK pin Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0. 2004 Microchip Technology Inc.
PIC16F7X7 11.4 AUSART Synchronous Slave Mode When setting up a Synchronous Slave Transmission, follow these steps: 1. Synchronous Slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in Sleep mode. Slave mode is entered by clearing bit, CSRC (TXSTA<7>). 11.4.1 2. 3. 4. 5.
PIC16F7X7 11.4.2 AUSART SYNCHRONOUS SLAVE RECEPTION When setting up a Synchronous Slave Reception, follow these steps: The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep mode. Bit SREN is a “don’t care” in Slave mode. 1. If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during Sleep.
PIC16F7X7 NOTES: DS30498C-page 150 2004 Microchip Technology Inc.
PIC16F7X7 12.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The Analog-to-Digital (A/D) Converter module has 11 inputs for the PIC16F737 and PIC16F767 devices and 14 for the PIC16F747 AND PIC16F777 devices. The A/D converter allows conversion of an analog input signal to a corresponding 10-bit digital number. A new feature for the A/D converter is the addition of programmable acquisition time. This feature allows the user to select a new channel for conversion and to set the GO/DONE bit immediately.
PIC16F7X7 REGISTER 12-1: ADCON0: A/D CONTROL REGISTER 0 (ADDRESS 1Fh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE CHS3 ADON bit 7 bit 0 bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits If ADCS2 = 0: 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC (clock derived from an RC oscillation) If ADCS2 = 1: 00 = FOSC/4 01 = FOSC/16 10 = FOSC/64 11 = FRC (clock derived from an RC oscillation) bit 5-3 CHS<2:0>: Analog Channel Select bits 0000 = Channe
PIC16F7X7 REGISTER 12-2: ADCON1: A/D CONTROL REGISTER 1 (ADDRESS 9Fh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM ADCS2 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. Six Most Significant bits of ADRESH are read as ‘0’. 0 = Left justified. Six Least Significant bits of ADRESL are read as ‘0’.
PIC16F7X7 REGISTER 12-3: ADCON2: A/D CONTROL REGISTER 2 (ADDRESS 9Bh) U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 — — ACQT2 ACQT1 ACQT0 — — — bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits 000 = 0(1) 001 = 2 TAD 010 = 4 TAD 011 = 6 TAD 100 = 8 TAD 101 = 12TAD 110 = 16 TAD 111 = 20 TAD Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
PIC16F7X7 The value in the ADRESH/ADRESL registers is not modified for a Power-on Reset. The ADRESH/ ADRESL registers will contain unknown data after a Power-on Reset. 2. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 12.1 “A/D Acquisition Requirements”.
PIC16F7X7 12.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 12-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 12-2.
PIC16F7X7 12.2 Selecting and Configuring Automatic Acquisition Time 12.3 The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as TAD. The A/D conversion requires a minimum 12 TAD per 10-bit conversion. The source of the A/D conversion clock is software selected.
PIC16F7X7 12.4 Operation in Power-Managed Modes The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode. If the A/D is expected to operate while the device is in a power-managed mode, the ACQT2:ACQT0 (ADCON2<5:3>) and ADCS2:ADCS0 (ADCON1<6>, ADCON0<7:6>) bits should be updated in accordance with the power-managed mode clock that will be used.
PIC16F7X7 12.6 A/D Conversions Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D conversion sample. This means the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). Figure 12-3 shows the operation of the A/D converter after the GO/DONE bit has been set and the ACQT2:ACQT0 bits are cleared.
PIC16F7X7 12.7 A/D Operation During Sleep 12.8 The A/D module can operate during Sleep mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed which eliminates all digital switching noise from the conversion. When the conversion is completed, the GO/DONE bit will be cleared and the result loaded into the ADRESH register.
PIC16F7X7 13.0 COMPARATOR MODULE The comparator module contains two analog comparators. The inputs to the comparators are multiplexed with I/O port pins, RA0 through RA3, while the outputs are multiplexed to pins RA4 and RA5. The on-chip voltage reference (Section 14.0 “Comparator Voltage Reference Module”) can also be an input to the comparators. REGISTER 13-1: The CMCON register (Register 13-1) controls the comparator input and output multiplexers.
PIC16F7X7 13.1 Comparator Configuration There are eight modes of operation for the comparators. The CMCON register is used to select these modes. Figure 13-1 shows the eight possible modes. The TRISA register controls the data direction of the comparator pins for each mode.
PIC16F7X7 13.2 13.3.2 Comparator Operation INTERNAL REFERENCE SIGNAL A single comparator is shown in Figure 13-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level.
PIC16F7X7 FIGURE 13-3: COMPARATOR OUTPUT BLOCK DIAGRAM Port pins MULTIPLEX + CxINV To RA4 or RA5 pin Bus Data Q Read CMCON Set CMIF bit D EN Q From other Comparator D EN CL Read CMCON Reset 13.6 Comparator Interrupts The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred.
PIC16F7X7 13.7 Comparator Operation During Sleep 13.9 When a comparator is active and the device is placed in Sleep mode, the comparator remains active and the interrupt is functional if enabled. This interrupt will wake-up the device from Sleep mode when enabled. While the comparator is powered up, higher Sleep currents than shown in the power-down current specification will occur. Each operational comparator will consume additional current as shown in the comparator specifications.
PIC16F7X7 NOTES: DS30498C-page 166 2004 Microchip Technology Inc.
PIC16F7X7 14.0 COMPARATOR VOLTAGE REFERENCE MODULE The comparator voltage reference generator is a 16-tap resistor ladder network that provides a fixed voltage reference when the comparators are in mode ‘110’. A programmable register controls the function of the reference generator. Register 14-1 lists the bit functions of the CVRCON register.
PIC16F7X7 FIGURE 14-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VDD 16 Stages CVREN 8R R R R R 8R CVRR RA2/AN2/VREF-/CVREF CVROE CVREF Input to Comparator TABLE 14-1: Address CVR3 CVR2 CVR1 CVR0 16:1 Analog MUX REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Value on POR Value on all other Resets Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9Dh CVRCON CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0 000- 0000 000- 0000 9Ch CMCON C2OUT C1OUT C2INV C1INV CIS
PIC16F7X7 15.
PIC16F7X7 REGISTER 15-1: R/P-1 R/P-1 CP CONFIGURATION WORD REGISTER 1 (ADDRESS 2007h) R/P-1 CCPMX DEBUG U-1 U-1 — — R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 BORV1 BORV0 BOREN MCLRE FOSC2 PWRTEN WDTEN FOSC1 FOSC0 bit 13 bit 0 bit 13 CP: Flash Program Memory Code Protection bits 1 = Code protection off 0 = 0000h to 1FFFh code-protected for PIC16F767/777 and 0000h to 0FFFh for PIC16F737/747 (all protected) bit 12 CCPMX: CCP2 Multiplex bit 1 = CCP2 is on RC1 0 = CCP2 is on RB
PIC16F7X7 REGISTER 15-2: CONFIGURATION WORD REGISTER 2 (ADDRESS 2008h) U-1 U-1 U-1 U-1 U-1 U-1 U-1 R/P-1 U-1 U-1 U-1 U-1 — — — — — — — BORSEN — — — — R/P-1 R/P-1 IESO FCMEN bit 13 bit 0 bit 13-7 Unimplemented: Read as ‘1’ bit 6 BORSEN: Brown-out Reset Software Enable bit Refer to Configuration Word Register 1, bit 6 for the function of this bit.
PIC16F7X7 15.2 Reset The PIC16F7X7 differentiates between various kinds of Reset: • • • • • • Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset during normal operation WDT Wake-up during Sleep Brown-out Reset (BOR) Some registers are not affected in any Reset condition. Their status is unknown on POR and unchanged in any other Reset.
PIC16F7X7 15.3 MCLR 15.5 PIC16F7X7 devices have a noise filter in the MCLR Reset path. This filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. The behavior of the ESD protection on the MCLR pin has been altered from previous devices of this family. Voltages applied to the pin that exceed its specification can result in both MCLR and excessive current, beyond the device specification, during the ESD event.
PIC16F7X7 15.8 Low-Voltage Detect In many applications, the ability to determine if the device voltage (VDD) is below a specified voltage level is a desirable feature. A window of operation for the application can be created where the application software can do “housekeeping tasks” before the device voltage exits the valid operating range. This can be done using the Low-Voltage Detect module. This module is a software programmable circuitry where a device voltage trip point can be specified.
PIC16F7X7 FIGURE 15-4: LOW-VOLTAGE DETECT (LVD) BLOCK DIAGRAM LVDIN LVD Control Register 16-to-1 MUX VDD Internally Generated Reference Voltage 1.2V LVDEN The LVD module has an additional feature that allows the user to supply the sense voltage to the module from an external source. This mode is enabled when bits LVDL3:LVDL0 are set to ‘1111’. In this state, the comparator input is multiplexed from the external input FIGURE 15-5: LVDIF pin, LVDIN (Figure 15-5).
PIC16F7X7 15.9 Control Register The Low-Voltage Detect Control register controls the operation of the Low-Voltage Detect circuitry.
PIC16F7X7 15.10 Operation The following steps are needed to set up the LVD module: Depending on the power source for the device voltage, the voltage normally decreases relatively slowly. This means that the LVD module does not need to be constantly operating. To decrease the current requirements, the LVD circuitry only needs to be enabled for short periods where the voltage is checked. After doing the check, the LVD module may be disabled. 1. 2. 3.
PIC16F7X7 15.10.1 REFERENCE VOLTAGE SET POINT The internal reference voltage of the LVD module may be used by other internal circuitry (the Programmable Brown-out Reset). If these circuits are disabled (lower current consumption), the reference voltage circuit requires a time to become stable before a low-voltage condition can be reliably detected. This time is invariant of system clock speed. This start-up time is specified in electrical specification parameter #36.
PIC16F7X7 TABLE 15-1: TIME-OUT IN VARIOUS SITUATIONS Power-up Oscillator Configuration PWRTE = 0 TPWRT XT, HS, LP EXTRC, INTRC + 1024 • TOSC Note 1: PWRTE = 1 PWRTE = 0 PWRTE = 1 Wake-up from Sleep 1024 • TOSC TPWRT + 1024 • TOSC 1024 • TOSC 1024 • TOSC 5-10 µs TPWRT T1OSC Brown-out Reset — (1) 5-10 µs TPWRT — — — (1) 5-10 µs(1) 5-10 µs(1) CPU start-up is always invoked on POR, BOR and wake-up from Sleep. The 5 µs-10 µs delay is based on a 1 MHz system clock.
PIC16F7X7 TABLE 15-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register W Power-on Reset, Brown-out Reset MCLR Reset, WDT Reset Wake-up via WDT or Interrupt xxxx xxxx uuuu uuuu uuuu uuuu INDF N/A N/A N/A TMR0 xxxx xxxx uuuu uuuu uuuu uuuu 0000h 0000h PC + 1(2) PCL STATUS 0001 1xxx 000q quuu(3) uuuq quuu(3) FSR xxxx xxxx uuuu uuuu uuuu uuuu PORTA xx0x 0000 uu0u 0000 uuuu uuuu PORTB xx00 0000 uu00 0000 uuuu uuuu PORTC xxxx xxxx uuuu uuuu uuuu uuuu PORTD xxxx xxxx u
PIC16F7X7 TABLE 15-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset MCLR Reset, WDT Reset Wake-up via WDT or Interrupt TRISA 1111 1111 1111 1111 uuuu uuuu TRISB 1111 1111 1111 1111 uuuu uuuu TRISC 1111 1111 1111 1111 uuuu uuuu TRISD 1111 1111 1111 1111 uuuu uuuu TRISE (PIC16F737/767) TRISE (PIC16F747/777) ---- 1--0000 1111 ---- u--0000 1111 ---- 1--uuuu uuuu PIE1 0000 0000 0000 0000 -uuu uuuu PIE2 000- 0-00 000- 0-00 uuu- u-uu PCON -
PIC16F7X7 FIGURE 15-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH PULL-UP RESISTOR) VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 15-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH RC NETWORK): CASE 1 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 15-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH RC NETWORK): CASE 2 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Inte
PIC16F7X7 FIGURE 15-10: SLOW RISE TIME (MCLR TIED TO VDD THROUGH RC NETWORK) 5V VDD 1V 0V MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset 2004 Microchip Technology Inc.
PIC16F7X7 15.15 Interrupts The PIC16F7X7 has up to 17 sources of interrupt. The Interrupt Control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. A Global Interrupt Enable bit, GIE (INTCON<7>), enables (if set) all unmasked interrupts or disables (if cleared) all interrupts.
PIC16F7X7 15.15.1 INT INTERRUPT 15.15.3 External interrupt on the RB0/INT pin is edge-triggered, either rising if bit INTEDG (OPTION_REG<6>) is set or falling if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INT0IF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit, INT0IE (INTCON<4>). Flag bit INT0IF must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt.
PIC16F7X7 15.17 Watchdog Timer (WDT) A new prescaler has been added to the path between the internal RC and the multiplexors used to select the path for the WDT. This prescaler is 16 bits and can be programmed to divide the internal RC by 32 to 65536, giving the time base used for the WDT a nominal range of 1 ms to 2.097s. For PIC16F7X7 devices, the WDT has been modified from previous PIC16 devices.
PIC16F7X7 REGISTER 15-4: WDTCON: WATCHDOG TIMER CONTROL REGISTER (ADDRESS 105h) U-0 U-0 U-0 R/W-0 — — — WDTPS3 R/W-1 R/W-0 R/W-0 R/W-0 WDTPS2 WDTPS1 WDTPS0 SWDTEN bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits 0000 = 1:32 Prescale rate 0001 = 1:64 Prescale rate 0010 = 1:128 Prescale rate 0011 = 1:256 Prescale rate 0100 = 1:512 Prescale rate 0101 = 1:1024 Prescale rate 0110 = 1:2048 Prescale rate 0111 = 1:4096 Prescale rate 1000 = 1:819
PIC16F7X7 15.17.3 TWO-SPEED CLOCK START-UP MODE Two-Speed Start-up minimizes the latency between oscillator start-up and code execution that may be selected with the IESO (Internal/External Switchover) bit in Configuration Word Register 2. This mode is achieved by initially using the INTRC for code execution until the primary oscillator is stable. If this mode is enabled and any of the following conditions exist, the system will begin execution with the INTRC oscillator.
PIC16F7X7 15.17.4 FAIL-SAFE OPTION The Fail-Safe Clock Monitor (FSCM) is designed to allow the device to continue to operate even in the event of an oscillator failure. FIGURE 15-14: FSCM BLOCK DIAGRAM Clock Monitor Latch (CM) (edge-triggered) Peripheral Clock S INTRC Oscillator ÷ 64 31.25 kHz (32 µs) 488 Hz (2.048 ms) C Q Q Clock Failure Detected The FSCM function is enabled by setting the FCMEN bit in Configuration Word Register 2.
PIC16F7X7 15.17.4.2 FSCM and the Watchdog Timer 15.18.1 WAKE-UP FROM SLEEP When a clock failure is detected, SCS<1:0> will be forced to ‘10’ which will reset the WDT (if enabled). The device can wake-up from Sleep through one of the following events: 15.17.4.3 1. 2. POR or Wake from Sleep The FSCM is designed to detect oscillator failure at any point after the device has exited Power-on Reset (POR) or low-power Sleep mode.
PIC16F7X7 15.18.2 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will not be cleared, the TO bit will not be set and the PD bit will not be cleared.
PIC16F7X7 15.19 In-Circuit Debugger 15.22 In-Circuit Serial Programming When the DEBUG bit in the Configuration Word is programmed to a ‘0’, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB® ICD. When the microcontroller has this feature enabled, some of the resources are not available for general use. Table 15-7 shows which features are consumed by the background debugger.
PIC16F7X7 16.0 INSTRUCTION SET SUMMARY The PIC16 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction.
PIC16F7X7 TABLE 16-2: PIC16F7X7 INSTRUCTION SET Mnemonic, Operands 14-Bit Opcode Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W t
PIC16F7X7 16.2 Instruction Descriptions ADDLW Add Literal and W BCF Bit Clear f Syntax: [ label ] ADDLW Syntax: [ label ] BCF Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: (W) + k → (W) Status Affected: C, DC, Z Operation: 0 → (f) Description: The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register. Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared.
PIC16F7X7 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 ≤ k ≤ 2047 Operands: None Operation: (PC) + 1 → TOS, k → PC<10:0>, (PCLATH<4:3>) → PC<12:11> Operation: Status Affected: None 00h → WDT 0 → WDT prescaler, 1 → TO 1 → PD Description: Call subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits<10:0>. The upper bits of the PC are loaded from PCLATH.
PIC16F7X7 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) – 1 → (destination); skip if result = 0 Operation: (f) + 1 → (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
PIC16F7X7 MOVF Move f Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: No operation Operation: (f) → (destination) Status Affected: None Status Affected: Z Description: No operation. Description: The contents of register ‘f’ are moved to a destination dependant upon the status of ‘d’. If d = 0, the destination is W register. If d = 1, the destination is file register ‘f’ itself. d = 1 is useful to test a file register since status flag Z is affected.
PIC16F7X7 RLF Rotate Left f through Carry SLEEP Enter Sleep mode Syntax: [ label ] RLF Syntax: [ label ] SLEEP Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: None Operation: Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC16F7X7 SWAPF Swap Nibbles in f XORWF Exclusive OR W with f Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORWF Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f<3:0>) → (destination<7:4>), (f<7:4>) → (destination<3:0>) Operation: (W) .XOR. (f) → (destination) Status Affected: Z Status Affected: None Description: Description: The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in the W register.
PIC16F7X7 17.
PIC16F7X7 17.3 MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 17.
PIC16F7X7 17.9 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator The MPLAB ICE 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers. Software control of the MPLAB ICE 2000 in-circuit emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
PIC16F7X7 17.14 PICSTART Plus Development Programmer 17.17 PICDEM 2 Plus Demonstration Board The PICSTART Plus development programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports most PICmicro devices up to 40 pins.
PIC16F7X7 17.20 PICDEM 17 Demonstration Board The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. A programmed sample is included. The PRO MATE II device programmer, or the PICSTART Plus development programmer, can be used to reprogram the device for user tailored application development.
PIC16F7X7 NOTES: DS30498C-page 206 2004 Microchip Technology Inc.
PIC16F7X7 18.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) .......................................... -0.
PIC16F7X7 FIGURE 18-1: PIC16F7X7 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL, EXTENDED) 6.0V 5.5V Voltage 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 16 MHz 20 MHz Frequency FIGURE 18-2: PIC16LF7X7 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 4 MHz 10 MHz Frequency FMAX = (12 MHz/V) (VDDAPPMIN – 2.5V) + 4 MHz Note 1: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application. Note 2: FMAX has a maximum frequency of 10 MHz.
PIC16F7X7 18.1 DC Characteristics: PIC16F737/747/767/777 (Industrial, Extended) PIC16LF737/747/767/777 (Industrial) PIC16LF737/747/767/777 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F737/747/767/777 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F7X7 18.2 DC Characteristics: Power-Down and Supply Current PIC16F737/747/767/777 (Industrial, Extended) PIC16LF737/747/767/777 (Industrial) PIC16LF737/747/767/777 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F737/747/767/777 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F7X7 18.2 DC Characteristics: Power-Down and Supply Current PIC16F737/747/767/777 (Industrial, Extended) PIC16LF737/747/767/777 (Industrial) (Continued) PIC16LF737/747/767/777 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F737/747/767/777 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F7X7 18.2 DC Characteristics: Power-Down and Supply Current PIC16F737/747/767/777 (Industrial, Extended) PIC16LF737/747/767/777 (Industrial) (Continued) PIC16LF737/747/767/777 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F737/747/767/777 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F7X7 18.2 DC Characteristics: Power-Down and Supply Current PIC16F737/747/767/777 (Industrial, Extended) PIC16LF737/747/767/777 (Industrial) (Continued) PIC16LF737/747/767/777 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F737/747/767/777 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F7X7 18.2 DC Characteristics: Power-Down and Supply Current PIC16F737/747/767/777 (Industrial, Extended) PIC16LF737/747/767/777 (Industrial) (Continued) PIC16LF737/747/767/777 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F737/747/767/777 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F7X7 18.2 DC Characteristics: Power-Down and Supply Current PIC16F737/747/767/777 (Industrial, Extended) PIC16LF737/747/767/777 (Industrial) (Continued) PIC16LF737/747/767/777 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F737/747/767/777 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F7X7 18.2 DC Characteristics: Power-Down and Supply Current PIC16F737/747/767/777 (Industrial, Extended) PIC16LF737/747/767/777 (Industrial) (Continued) PIC16LF737/747/767/777 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F737/747/767/777 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F7X7 18.3 DC Characteristics: Internal RC Accuracy PIC16F737/747/767/777 (Industrial, Extended) PIC16LF737/747/767/777 (Industrial) PIC16LF737/747/767/777 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F737/747/767/777 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F7X7 18.4 DC Characteristics: PIC16F737/747/767/777 (Industrial, Extended) PIC16LF737/747/767/777 (Industrial) DC CHARACTERISTICS Param Sym No. Min Typ† Max Units with TTL buffer VSS — 0.15 VDD V For entire VDD range VSS — 0.8V V 4.5V ≤ VDD ≤ 5.5V D031 with Schmitt Trigger buffer VSS — 0.2 VDD V D032 MCLR, OSC1 (in RC mode) VSS — 0.2 VDD V D033 OSC1 (in XT and LP modes) VSS — 0.3V V OSC1 (in HS mode) VSS — 0.
PIC16F7X7 18.4 DC Characteristics: PIC16F737/747/767/777 (Industrial, Extended) PIC16LF737/747/767/777 (Industrial) (Continued) DC CHARACTERISTICS Param Sym No. IIL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Operating voltage VDD range as described in Section 18.1 “DC Characteristics”.
PIC16F7X7 TABLE 18-1: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated). Param No. Sym Characteristics Min Typ Max Units D300 VIOFF Input Offset Voltage — ± 5.0 ± 10 mV D301 VICM Input Common Mode Voltage* 0 — VDD – 1.
PIC16F7X7 FIGURE 18-3: LOW-VOLTAGE DETECT CHARACTERISTICS VDD (LVDIF can be cleared in software) VLVD (LVDIF set by hardware) LVDIF TABLE 18-3: LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F7X7 18.5 Timing Parameter Symbology The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
PIC16F7X7 FIGURE 18-5: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 18-4: Param No. EXTERNAL CLOCK TIMING REQUIREMENTS Symbol FOSC Characteristic External CLKI Frequency (Note 1) Oscillator Frequency (Note 1) 1 TOSC External CLKI Period (Note 1) Oscillator Period (Note 1) Min Typ† Max Units Conditions DC — 1 MHz XT Oscillator mode DC — 20 MHz HS Oscillator mode DC — 32 kHz LP Oscillator mode DC — 4 MHz RC Oscillator mode 0.
PIC16F7X7 FIGURE 18-6: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 14 19 12 18 16 I/O pin (Input) 15 17 I/O pin (Output) New Value Old Value 20, 21 Note: Refer to Figure 18-4 for load conditions. TABLE 18-5: Param No.
PIC16F7X7 FIGURE 18-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 Oscillator Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure 18-4 for load conditions. FIGURE 18-8: BROWN-OUT RESET TIMING VBOR VDD 35 TABLE 18-6: Param No.
PIC16F7X7 FIGURE 18-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI/C1OUT 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 18-4 for load conditions. TABLE 18-7: Param No.
PIC16F7X7 FIGURE 18-10: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 51 50 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 54 53 Note: Refer to Figure 18-4 for load conditions. TABLE 18-8: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param Symbol No. 50* 51* TCCL TCCH Characteristic Min Typ† Max Units CCP1, CCP2 and No prescaler CCP3 Input Low With prescaler PIC16F7X7 Time PIC16LF7X7 0.
PIC16F7X7 FIGURE 18-11: PARALLEL SLAVE PORT TIMING (PIC16F747/777 DEVICES ONLY) RE2/CS/AN7 RE0/RD/AN5 RE1/WR/AN6 65 RD7/PSP7:RD0/PSP0 62 64 63 Note: Refer to Figure 18-4 for load conditions. TABLE 18-9: Param No.
PIC16F7X7 FIGURE 18-12: SPI™ MASTER MODE TIMING (CKE = 0, SMP = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO LSb bit 6 - - - - - -1 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure 18-4 for load conditions. FIGURE 18-13: SPI™ MASTER MODE TIMING (CKE = 1, SMP = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb LSb bit 6 - - - - - -1 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 Note: Refer to Figure 18-4 for load conditions.
PIC16F7X7 FIGURE 18-14: SPI™ SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO LSb bit 6 - - - - - -1 77 75, 76 SDI bit 6 - - - -1 MSb In LSb In 74 73 Note: Refer to Figure 18-4 for load conditions. FIGURE 18-15: SPI™ SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 SDO MSb bit 6 - - - - - -1 LSb 77 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 Note: Refer to Figure 18-4 for load conditions.
PIC16F7X7 TABLE 18-10: SPI™ MODE REQUIREMENTS Param No.
PIC16F7X7 TABLE 18-11: I2C™ BUS START/STOP BITS REQUIREMENTS Param Symbol No.
PIC16F7X7 TABLE 18-12: I2C™ BUS DATA REQUIREMENTS Param. No. 100* Symbol THIGH Characteristic Clock High Time Min Max Units 100 kHz mode 4.0 — µs Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — µs Device must operate at a minimum of 10 MHz 1.5 TCY — 100 kHz mode 4.7 — µs Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.
PIC16F7X7 FIGURE 18-18: RC6/TX/CK pin AUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure 18-4 for load conditions. TABLE 18-13: AUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No.
PIC16F7X7 TABLE 18-15: A/D CONVERTER CHARACTERISTICS: PIC16F7X7 (INDUSTRIAL, EXTENDED) PIC16LF7X7 (INDUSTRIAL) Param Sym No. Characteristic Min Typ† Max Units Conditions A01 NR Resolution — — 10 bits bit VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A03 EIL Integral Linearity Error — — <±1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A04 EDL Differential Linearity Error — — <±1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A06 EOFF Offset Error — — <±2 LSb VREF = VDD = 5.
PIC16F7X7 FIGURE 18-20: A/D CONVERSION TIMING 1 TCY BSF ADCON0, GO (TOSC/2)(1) 131 Q4 130 A/D CLK 132 9 A/D DATA 8 ... 7 ... 2 1 0 OLD_DATA ADRES NEW_DATA ADIF GO DONE Sampling Stopped SAMPLE Note: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 18-16: A/D CONVERSION REQUIREMENTS Param Symbol No. 130 TAD Characteristic A/D Clock Period — — µs TOSC based, VREF ≥ 3.
PIC16F7X7 19.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
PIC16F7X7 FIGURE 19-3: TYPICAL IDD vs. FOSC OVER VDD (XT MODE) 1.8 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 1.6 5.5V 1.4 5.0V 1.2 4.5V IDD (mA) 4.0V 1.0 3.5V 0.8 3.0V 2.5V 0.6 2.0V 0.4 0.2 0.0 0 500 1000 1500 2000 2500 3000 3500 4000 3500 4000 FOSC (MHz) FIGURE 19-4: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE) 2.
PIC16F7X7 FIGURE 19-5: TYPICAL IDD vs. FOSC OVER VDD (LP MODE) 70 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 60 5.5V 5.0V 50 4.5V IDD (µA) 40 4.0V 3.5V 30 3.0V 2.5V 20 2.0V 10 0 20 30 40 50 60 70 80 90 100 FOSC (kHz) FIGURE 19-6: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE) 120 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 5.5V 100 5.0V 4.5V 80 IDD (µA) 4.
PIC16F7X7 FIGURE 19-7: TYPICAL IDD vs. VDD, -40°C TO +125°C, 1 MHz TO 8 MHz (RC_RUN MODE, ALL PERIPHERALS DISABLED) 1.6 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 1.4 5.5V 5.0V 1.2 4.5V 1.0 IDD (mA) 4.0V 3.5V 0.8 3.0V 0.6 2.5V 0.4 2.0V 0.2 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 FOSC (MHz) FIGURE 19-8: MAXIMUM IDD vs. VDD, -40°C TO +125°C, 1 MHz TO 8 MHz (RC_RUN MODE, ALL PERIPHERALS DISABLED) 4.
PIC16F7X7 FIGURE 19-9: IDD vs. VDD, SEC_RUN MODE, -10°C TO +125°C, 32.768 kHz (XTAL 2 x 22 pF, ALL PERIPHERALS DISABLED) 45.0 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 40.0 35.0 Max (+70°C) IDD (µA) 30.0 25.0 Typ (+25°C) 20.0 15.0 10.0 5.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 19-10: IPD vs. VDD, -40°C TO +125°C (SLEEP MODE, ALL PERIPHERALS DISABLED) 100 Max (125°C) 10 Max (85°C) IPD (µA) 1 0.1 0.
PIC16F7X7 FIGURE 19-11: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 20 pF, +25°C) 4.5 Operation above 4 MHz is not recommended 4.0 5.1 kOhm 3.5 Freq (MHz) 3.0 2.5 10 kOhm 2.0 1.5 1.0 0.5 100 kOhm 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 19-12: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 100 pF, +25°C) 2.5 2.0 3.3 kOhm Freq (MHz) 1.5 5.1 kOhm 1.0 10 kOhm 0.5 100 kOhm 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16F7X7 FIGURE 19-13: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 300 pF, +25°C) 0.9 0.8 3.3 kOhm 0.7 0.6 Freq (MHz) 5.1 kOhm 0.5 0.4 10 kOhm 0.3 0.2 0.1 100 kOhm 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 19-14: ∆IPD TIMER1 OSCILLATOR, -10°C TO +70°C (SLEEP MODE, TMR1 COUNTER DISABLED) IPD Timer1 Oscillator, -10°C to +70°C SLEEP mode, TMR1 counter disabled 5.0 4.5 Max (-10°C to +70°C) 4.0 3.5 3.0 IPD (µA) Typ (+25°C) 2.5 2.0 1.
PIC16F7X7 FIGURE 19-15: ∆IPD WDT, -40°C TO +125°C (SLEEP MODE, ALL PERIPHERALS DISABLED) 18 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 16 14 ∆IWDT (µA) 12 10 Max (-40°C to +125°C) 8 6 Max (-40°C to +85°C) 4 2 Typ (25°C) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 19-16: ∆IPD LVD vs. VDD (SLEEP MODE, LVD = 2.00V-2.
PIC16F7X7 FIGURE 19-17: ∆IPD BOR vs. VDD, -40°C TO +125°C (SLEEP MODE, BOR ENABLED AT 2.00V-2.16V) 40 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 35 Max (+125°C) 30 25 IPD (µA) Typ (+25°C) 20 15 10 Device may be in Reset 5 Device is Operating 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16F7X7 FIGURE 19-19: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40°C TO +125°C) 5.5 5.0 4.5 4.0 Max 3.5 VOH (V) Typ (25°C) 3.0 2.5 Min 2.0 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 1.5 1.0 0.5 0.0 0 5 10 15 20 25 IOH (-mA) FIGURE 19-20: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40°C TO +125°C) 3.
PIC16F7X7 FIGURE 19-21: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 5V, -40°C TO +125°C) 1.0 0.9 Max (125°C) Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 0.8 0.7 Max (85°C) VOL (V) 0.6 0.5 Typ (25°C) 0.4 0.3 Min (-40°C) 0.2 0.1 0.0 0 5 10 15 20 25 IOL (-mA) FIGURE 19-22: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 3V, -40°C TO +125°C) 3.
PIC16F7X7 FIGURE 19-23: MINIMUM AND MAXIMUM VIN vs. VDD (TTL INPUT, -40°C TO +125°C) 1.5 1.4 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 1.3 VTH Max (-40°C) 1.2 1.1 VIN (V) VTH Typ (25°C) 1.0 VTH Min (125°C) 0.9 0.8 0.7 0.6 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 19-24: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40°C TO +125°C) 4.
PIC16F7X7 MINIMUM AND MAXIMUM VIN vs. VDD (I2C™ INPUT, -40°C TO +125°C) FIGURE 19-25: 3.5 VIH Max Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 3.0 2.5 2.0 VIN (V) V Max VIL ILMax VIH Min 1.5 1.0 VIL Min 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 19-26: A/D NONLINEARITY vs. VREFH (VDD = VREFH, -40°C TO +125°C) 4 3.5 Differential or Integral Nonlinearity (LSB) -40°C -40C 3 +25°C 25C 2.5 +85°C 85C 2 1.5 1 0.
PIC16F7X7 FIGURE 19-27: A/D NONLINEARITY vs. VREFH (VDD = 5V, -40°C TO +125°C) 3 Differential or Integral Nonlinearilty (LSB) 2.5 2 1.5 Max +125°C) Max (-40°C (-40C toto125C) 1 Typ Typ (+25°C) (25C) 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 VREFH (V) DS30498C-page 250 2004 Microchip Technology Inc.
PIC16F7X7 20.0 PACKAGING INFORMATION 20.1 Package Marking Information 28-Lead PDIP (Skinny DIP) Example PIC16F737-I/SP 0410017 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SSOP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 28-Lead QFN Legend: XX...
PIC16F7X7 Package Marking Information (Continued) 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead QFN XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS30498C-page 252 PIC16F777-I/P 0410017 Example PIC16F777 -I/PT 0410017 Example PIC16F777 -I/ML 0410017 2004 Microchip Technology Inc.
PIC16F7X7 20.2 Package Details The following sections give the technical details of the packages. 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil Body (PDIP) E1 D 2 n 1 α E A2 A L c β B1 A1 eB Units Number of Pins Pitch p B Dimension Limits n p INCHES* MIN NOM MILLIMETERS MAX MIN NOM 28 MAX 28 .100 2.54 Top to Seating Plane A .140 .150 .160 3.56 3.81 4.06 Molded Package Thickness A2 .125 .130 .135 3.18 3.30 3.43 8.26 Base to Seating Plane A1 .
PIC16F7X7 28-Lead Plastic Small Outline (SO) – Wide, 300 mil Body (SOIC) E E1 p D B 2 1 n h α 45° c A2 A φ β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Top Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L φ c B α β A1 MIN .093 .088 .004 .394 .288 .695 .
PIC16F7X7 28-Lead Plastic Shrink Small Outline (SS) – 209 mil Body, 5.30 mm (SSOP) E E1 p D B 2 1 n A c A2 f A1 L Units Dimension Limits n p MIN INCHES NOM 28 .026 .069 .307 .209 .402 .030 4° - MAX MILLIMETERS* NOM 28 0.65 1.65 1.75 0.05 7.49 7.80 5.00 5.30 9.90 10.20 0.55 0.75 0.09 0° 4° 0.22 - MIN Number of Pins Pitch Overall Height A .079 Molded Package Thickness A2 .065 .073 Standoff A1 .002 Overall Width E .295 .323 Molded Package Width E1 .009 .220 Overall Length D .390 .
PIC16F7X7 28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body (QFN) – With 0.55 mm Contact Length (Saw Singulated) E E2 EXPOSED METAL PAD e D D2 b 2 1 n OPTIONAL INDEX AREA TOP VIEW ALTERNATE INDEX INDICATORS SEE DETAIL L BOTTOM VIEW A1 A DETAIL ALTERNATE PAD OUTLINE Number of Pins Pitch Overall Height Standoff Contact Thickness Overall Width Exposed Pad Width Overall Length Exposed Pad Length Contact Width Contact Length Units Dimension Limits n e A A1 A3 E E2 D D2 b L MIN .031 .
PIC16F7X7 40-Lead Plastic Dual In-line (P) – 600 mil Body (PDIP) E1 D α 2 1 n E A2 A L c β B1 A1 eB p B Units Dimension Limits n p MIN INCHES* NOM 40 .100 .175 .150 MAX MILLIMETERS NOM 40 2.54 4.06 4.45 3.56 3.81 0.38 15.11 15.24 13.46 13.84 51.94 52.26 3.05 3.30 0.20 0.29 0.76 1.27 0.36 0.46 15.75 16.51 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .160 .190 Molded Package Thickness A2 .140 .160 Base to Seating Plane .015 A1 Shoulder to Shoulder Width E .595 .600 .
PIC16F7X7 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.
PIC16F7X7 44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN) 2004 Microchip Technology Inc.
PIC16F7X7 NOTES: DS30498C-page 260 2004 Microchip Technology Inc.
PIC16F7X7 APPENDIX A: REVISION HISTORY Revision A (June 2003) This is a new data sheet. However, these devices are similar to the PIC16C7X devices found in the PIC16C7X Data Sheet (DS30390) or the PIC16F87X devices (DS30292). APPENDIX B: DEVICE DIFFERENCES The differences between the devices in this data sheet are listed in Table B-1. Revision B (November 2003) This revision includes updates to the Electrical Specifications in Section 18.
PIC16F7X7 APPENDIX C: CONVERSION CONSIDERATIONS Considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in Table C-1.
PIC16F7X7 INDEX A Asynchronous Transmission Associated Registers........................................ 139 Setup ................................................................ 139 Baud Rate Generator (BRG) .................................... 135 Associated Registers........................................ 135 Baud Rate Formula .......................................... 135 Baud Rates, Asynchronous Mode (BRGH = 0)...............................................
PIC16F7X7 Block Diagrams A/D ............................................................................ 155 Analog Input Model ........................................... 156, 165 AUSART Receive ............................................. 140, 142 AUSART Transmit .................................................... 138 Baud Rate Generator ................................................ 119 Capture Mode Operation ............................................ 89 Comparator I/O Operating Modes.............
PIC16F7X7 Comparator Module .......................................................... 161 Analog Input Connection Considerations .................................................. 165 Associated Registers ................................................ 165 Configuration............................................................. 162 Effects of a Reset...................................................... 165 Interrupts................................................................... 164 Operation .....
PIC16F7X7 CLRW ....................................................................... 196 CLRWDT................................................................... 196 COMF ....................................................................... 196 DECF ........................................................................ 196 DECFSZ.................................................................... 197 Firmware Instructions................................................ 193 General Format ............
PIC16F7X7 Oscillator Control Register Modifying IRCF Bits .................................................... 39 Clock Transition Sequence ................................. 40 Oscillator Delay upon Power-up, Wake-up and Clock Switching.................................................... 40 Oscillator Start-up Timer (OST) ................................ 169, 173 Oscillator Switching............................................................. 37 P Packaging ................................................
PIC16F7X7 R RA0/AN0 Pin ................................................................... 8, 11 RA1/AN1 Pin ................................................................... 8, 11 RA2/AN2/VREF-/CVREF Pin ............................................. 8, 11 RA3/AN3/VREF+ Pin........................................................ 8, 11 RA4/T0CKI/C1OUT Pin................................................... 8, 11 RA5/AN4/LVDIN/SS/C2OUT Pin .................................... 8, 11 RAM. See Data Memory.
PIC16F7X7 SS ....................................................................................... 93 SSPBUF.............................................................................. 98 SSPIF Bit ............................................................................ 25 SSPOV.............................................................................. 123 SSPOV Status Flag .......................................................... 123 SSPSR .......................................................
PIC16F7X7 Parallel Slave Port Write ............................................. 71 PWM Output ............................................................... 91 Repeated Start Condition.......................................... 122 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer ................................................ 225 Slave Mode General Call Address Sequence (7 or 10-Bit Address Mode)............................... 116 Slave Synchronization (SPI Mode) .....................
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PIC16F7X7 PIC16F7X7 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX XXX Package Pattern Examples: a) b) Device PIC16F7X7(1), PIC16F7X7T(1); VDD range 4.0V to 5.5V PIC16LF7X7(1), PIC16LF7X7T(1); VDD range 2.0V to 5.5V Temperature Range I E = = c) PIC16F777-I/P 301 = Industrial temp., PDIP package, normal VDD limits, QTP pattern #301.
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