Datasheet
PIC16F7X
DS30325B-page 18 2002 Microchip Technology Inc.
Bank 2
100h
(4)
INDF Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 27, 96
101h TMR0 Timer0 Module Register
xxxx xxxx 45, 96
102h
(4)
PCL Program Counter (PC) Least Significant Byte
0000 0000 26, 96
103h
(4)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 19, 96
104h
(4)
FSR Indirect Data Memory Address Pointer
xxxx xxxx 27, 96
105h — Unimplemented
— —
106h PORTB PORTB Data Latch when written: PORTB pins when read
xxxx xxxx 34, 96
107h — Unimplemented
— —
108h — Unimplemented
— —
109h — Unimplemented — —
10Ah
(1,4)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter
---0 0000 21, 96
10Bh
(4)
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF
0000 000x 23, 96
10Ch PMDATA Data Register Low Byte xxxx xxxx 29, 97
10Dh PMADR Address Register Low Byte
xxxx xxxx 29, 97
10Eh PMDATH — — Data Register High Byte
xxxx xxxx 29, 97
10Fh PMADRH — — — Address Register High Byte
xxxx xxxx
29, 97
Bank 3
180h
(4)
INDF Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 27, 96
181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
1111 1111 20, 44, 96
182h
(4)
PCL Program Counter (PC) Least Significant Byte 0000 0000 26, 96
183h
(4)
STATUS IRP RP1 RP0 TO PD ZDCC
0001 1xxx 19, 96
184h
(4)
FSR Indirect Data Memory Address Pointer xxxx xxxx 27, 96
185h — Unimplemented — —
186h TRISB PORTB Data Direction Register 1111 1111 34, 96
187h — Unimplemented
— —
188h — Unimplemented
— —
189h — Unimplemented
— —
18Ah
(1,4)
PCLATH — — —
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 21, 96
18Bh
(4)
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF
0000 000x 23, 96
18Ch PMCON1
—
(6)
— — — — — — RD
1--- ---0 29, 97
18Dh — Unimplemented
—
18Eh — Reserved maintain clear
0000 0000
18Fh — Reserved maintain clear
0000 0000
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Details
on page
Legend:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter during branches (
CALL or GOTO).
2: Other (non power-up) RESETS include external RESET through MCLR
and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.