Datasheet

 2002 Microchip Technology Inc. DS30325B-page 167
PIC16F7X
S
S (START) bit .................................................................... 60
SCI. See USART
SCL
.................................................................................... 65
Serial Communication Interface. See USART
SLEEP
................................................................89, 93, 102
SMP bit
..............................................................................60
Software Simulator (MPLAB SIM)
................................... 114
Special Features of the CPU
.............................................89
Special Function Registers
...................................16, 16–18
Speed, Operating
................................................................. 1
SPI Mode
........................................................................... 59
Associated Registers
.................................................64
Serial Clock (SCK pin)
...............................................59
Serial Data In (SDI pin)
.............................................. 59
Serial Data Out (SDO pin)
.........................................59
Slave Select
...............................................................59
SSP
Overview
RA5/SS
/AN4 Pin ................................................... 8, 10
RC3/SCK/SCL Pin
................................................ 9, 11
RC4/SDI/SDA Pin
................................................. 9, 11
RC5/SDO Pin
....................................................... 9, 11
SSP I
2
C Operation .............................................................65
Slave Mode
................................................................ 65
SSPEN bit
.......................................................................... 61
SSPIF bit
............................................................................ 23
SSPM<3:0> bits
................................................................. 61
SSPOV bit
.......................................................................... 61
Stack
..................................................................................26
Overflows
................................................................... 26
Underflow
.................................................................. 26
STATUS Register
DC Bit
........................................................................ 19
IRP Bit
.......................................................................19
PD
Bit ........................................................................ 93
TO
Bit ................................................................. 19, 93
Z Bit
...........................................................................19
Synchronous Serial Port Enable bit (SSPEN)
................... 61
Synchronous Serial Port Interrupt bit (SSPIF)
................... 23
Synchronous Serial Port Mode Select bits
(SSPM<3:0>)
.............................................................61
Synchronous Serial Port. See SSP
T
T1CKPS0 bit ......................................................................47
T1CKPS1 bit
...................................................................... 47
T1OSCEN bit
..................................................................... 47
T1SYNC
bit ........................................................................ 47
T2CKPS0 bit
...................................................................... 52
T2CKPS1 bit
...................................................................... 52
T
AD ..................................................................................... 87
Time-out Sequence
...........................................................94
Timer0
................................................................................43
Associated Registers
.................................................45
Clock Source Edge Select (T0SE bit)
........................ 20
Clock Source Select (T0CS bit)
................................. 20
External Clock
...........................................................44
Interrupt
.....................................................................43
Overflow Enable (TMR0IE bit)
................................... 21
Overflow Flag (TMR0IF bit)
..................................... 100
Overflow Interrupt
....................................................100
Prescaler
................................................................... 45
RA4/T0CKI Pin, External Clock
............................ 8, 10
T0CKI
........................................................................ 44
Timer1
............................................................................... 47
Associated Registers
................................................ 50
Asynchronous Counter Mode
.................................... 49
Capacitor Selection
................................................... 50
Counter Operation
..................................................... 48
Operation in Timer Mode
.......................................... 48
Oscillator
................................................................... 50
Prescaler
................................................................... 50
RC0/T1OSO/T1CKI Pin
........................................9, 11
RC1/T1OSI/CCP2 Pin
...........................................9, 11
Resetting of Timer1 Registers
................................... 50
Resetting Timer1 using a CCP Trigger Output
......... 50
Synchronized Counter Mode
..................................... 48
TMR1H Register
....................................................... 49
TMR1L Register
........................................................ 49
Timer2
............................................................................... 51
Associated Registers
................................................ 52
Output
....................................................................... 51
Postscaler
................................................................. 51
Prescaler
................................................................... 51
Prescaler and Postscaler
.......................................... 51
Timing Diagrams
A/D Conversion
....................................................... 139
Brown-out Reset
..................................................... 128
Capture/Compare/PWM (CCP1 and CCP2)
........... 130
CLKOUT and I/O
..................................................... 127
External Clock
......................................................... 126
I
2
C Bus Data ........................................................... 135
I
2
C Bus START/STOP bits ...................................... 134
I
2
C Reception (7-bit Address) ................................... 67
I
2
C Transmission (7-bit Address) .............................. 67
Parallel Slave Port
................................................... 131
Parallel Slave Port Read Waveforms
........................ 41
Parallel Slave Port Write Waveforms
........................ 41
Power-up Timer
....................................................... 128
PWM Output
.............................................................. 57
RESET
.................................................................... 128
Slow Rise Time (MCLR
Tied to VDD Through
RC Network)
............................................. 98
SPI Master Mode (CKE = 0, SMP = 0)
.................... 132
SPI Master Mode (CKE = 1, SMP = 1)
.................... 132
SPI Mode (Master Mode)
.......................................... 63
SPI Mode (Slave Mode with CKE = 0)
...................... 63
SPI Mode (Slave Mode with CKE = 1)
...................... 63
SPI Slave Mode (CKE = 0)
...................................... 133
SPI Slave Mode (CKE = 1)
...................................... 133
Start-up Timer
......................................................... 128
Time-out Sequence on Power-up (MCLR
Not
Tied to V
DD)
Case 1
............................................................... 98
Case 2
............................................................... 98
Time-out Sequence on Power-up (MCLR
Tied to Vdd
Through RC Network)
............................... 97
Timer0
..................................................................... 129
Timer1
..................................................................... 129
USART Asynchronous Master Transmission
............ 74
USART Asynchronous Master Transmission
(Back to Back)
........................................... 74
USART Asynchronous Reception
............................. 76
USART Synchronous Receive (Master/Slave)
........ 137
USART Synchronous Reception
(Master Mode, SREN)
............................... 79
USART Synchronous Transmission
.......................... 78
USART Synchronous Transmission
(Master/Slave)
......................................... 137