M PIC16F7X Data Sheet 28/40-pin, 8-bit CMOS FLASH Microcontrollers 2002 Microchip Technology Inc.
Note the following details of the code protection feature on PICmicro® MCUs. • • • • • • The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature.
M PIC16F7X 28/40-Pin 8-Bit CMOS FLASH Microcontrollers Devices Included in this Data Sheet: Peripheral Features: • High performance RISC CPU • Only 35 single word instructions to learn • All single cycle instructions except for program branches which are two-cycle • Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle • Up to 8K x 14 words of FLASH Program Memory, Up to 368 x 8 bytes of Data Memory (RAM) • Pinout compatible to the PIC16C73B/74B/76/77 • Pinout compatible to the PIC16F8
PIC16F7X Pin Diagrams DIP, SOIC, SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7/PGD RB6/PGC RB5 RB4 RB3/PGM RB2 RB1 RB0/INT VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RA1/AN1 RA0/AN0 MCLR/VPP RB7/PGD RB6/PGC RB5 RB4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC16F76/73 MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL MLF 1 2 3 4 5 6 7 28 27 26 25 24 23 22 21 20 PIC16F73 19 18 PIC16F76 17 16 15 8 9 10 11
PIC16F7X Pin Diagrams (Continued) PIC16F77 PIC16F74 39 38 37 36 35 34 33 32 31 30 9 18 19 20 21 22 23 24 25 26 27 282 7 8 9 10 11 12 13 14 15 16 17 RB3/PGM RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RC4/SDI/SDA RC5/SDO RC6/TX/CK NC RA4/T0CKI RA5/AN4/SS RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CK1 NC 6 5 4 3 2 1 44 43 42 41 40 RA3/AN3/VREF RA2/AN2 RA1/AN1 RA0/AN0 MCLR
PIC16F7X Table of Contents 1.0 Device Overview ......................................................................................................................................................................... 5 2.0 Memory Organization................................................................................................................................................................ 13 3.0 Reading Program Memory................................................................................
PIC16F7X 1.0 DEVICE OVERVIEW This document contains device specific information about the following devices: • • • • PIC16F73 PIC16F74 PIC16F76 PIC16F77 PIC16F73/76 devices are available only in 28-pin packages, while PIC16F74/77 devices are available in 40-pin and 44-pin packages. All devices in the PIC16F7X family share common architecture, with the following differences: The available features are summarized in Table 1-1.
PIC16F7X FIGURE 1-1: PIC16F73 AND PIC16F76 BLOCK DIAGRAM 13 FLASH Program Memory 14 PORTA RA0/AN0 RA1/AN1 RA2/AN2/ RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS RAM File Registers 8 Level Stack (13-bit) Program Bus 8 Data Bus Program Counter RAM Addr(1) 9 PORTB Addr MUX Instruction reg Direct Addr 7 8 Indirect Addr FSR reg STATUS reg 8 RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD PORTC 3 Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Tim
PIC16F7X FIGURE 1-2: PIC16F74 AND PIC16F77 BLOCK DIAGRAM 13 FLASH Program Memory PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS RAM File Registers 8 Level Stack (13-bit) Program Bus 8 Data Bus Program Counter 14 RAM Addr(1) PORTB 9 RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD Addr MUX Instruction reg Direct Addr 7 8 Indirect Addr FSR reg STATUS reg 8 PORTC 3 Power-up Timer Instruction Decode & Control Oscillator Start-up Timer Timing Generation Watchdog Timer Brow
PIC16F7X TABLE 1-2: Pin Name OSC1/CLKI OSC1 PIC16F73 AND PIC16F76 PINOUT DESCRIPTION DIP SSOP SOIC Pin# MLF Pin# 9 6 I CLKI OSC2/CLKO OSC2 I 10 7 Buffer Type — Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. ST Master Clear (input) or programming voltage (output). Master Clear (Reset) input.
PIC16F7X TABLE 1-2: PIC16F73 AND PIC16F76 PINOUT DESCRIPTION (CONTINUED) Pin Name DIP SSOP SOIC Pin# MLF Pin# I/O/P Type Buffer Type Description PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT RB0 INT 21 TTL/ST(1) 18 I/O I Digital I/O. External interrupt. RB1 22 19 I/O TTL Digital I/O. RB2 23 20 I/O TTL Digital I/O. RB3/PGM RB3 PGM 24 21 TTL I/O I/O Digital I/O. Low voltage ICSP programming enable pin.
PIC16F7X TABLE 1-3: Pin Name OSC1/CLKI OSC1 PIC16F74 AND PIC16F77 PINOUT DESCRIPTION DIP Pin# PLCC Pin# QFP Pin# 13 14 30 I/O/P Type I CLKI I OSC2/CLKO OSC2 14 15 31 Buffer Type ST/CMOS(4) Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode. Otherwise CMOS. External clock source input. Always associated with pin function OSC1 (see OSC1/CLKI, OSC2/CLKO pins). — Oscillator crystal or clock output.
PIC16F7X TABLE 1-3: PIC16F74 AND PIC16F77 PINOUT DESCRIPTION (CONTINUED) Pin Name DIP Pin# PLCC Pin# QFP Pin# I/O/P Type Buffer Type Description PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT RB0 INT 33 36 TTL/ST(1) 8 I/O I Digital I/O. External interrupt. RB1 34 37 9 I/O TTL Digital I/O. RB2 35 38 10 I/O TTL Digital I/O. RB3/PGM RB3 PGM 36 39 11 RB4 37 41 14 I/O TTL Digital I/O.
PIC16F7X TABLE 1-3: Pin Name PIC16F74 AND PIC16F77 PINOUT DESCRIPTION (CONTINUED) DIP Pin# PLCC Pin# QFP Pin# I/O/P Type Buffer Type Description PORTD is a bi-directional I/O port or parallel slave port when interfacing to a microprocessor bus.
PIC16F7X 2.0 MEMORY ORGANIZATION There are two memory blocks in each of these PICmicro® MCUs. The Program Memory and Data Memory have separate buses so that concurrent access can occur and is detailed in this section. The Program Memory can be read internally by user code (see Section 3.0). 2.2 The Data Memory is partitioned into multiple banks, which contain the General Purpose Registers and the Special Function Registers.
PIC16F7X FIGURE 2-2: PIC16F77/76 REGISTER FILE MAP Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(1) PORTE(1) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRES ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h Indirect addr.
PIC16F7X FIGURE 2-3: PIC16F74/73 REGISTER FILE MAP File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(1) PORTE(1) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRES ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h File Address Indirect addr.
PIC16F7X 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in the peripheral feature section. The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device.
PIC16F7X TABLE 2-1: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on page 0000 0000 27, 96 Bank 1 80h(4) INDF 81h OPTION_REG 82h(4) PCL 83h(4) STATUS Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 PD Z DC C 1111 1111 20, 44, 96 Program Counter’s (PC) Least Significant Byte IRP RP1 RP0 TO 0000 0000
PIC16F7X TABLE 2-1: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on page Bank 2 100h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 27, 96 101h TMR0 Timer0 Module Register xxxx xxxx 45, 96 102h(4) PCL Program Counter (PC) Least Significant Byte 0000 0000 26, 96 103h(4) STATUS 0001 1xxx 19, 96 104h(4) FSR Indirect Data Mem
PIC16F7X 2.2.2.1 STATUS Register The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC, or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
PIC16F7X 2.2.2.2 OPTION_REG Register Note: The OPTION_REG register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 2-2: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer.
PIC16F7X 2.2.2.3 INTCON Register Note: The INTCON register is a readable and writable register, which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts. REGISTER 2-3: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16F7X 2.2.2.4 PIE1 Register Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. The PIE1 register contains the individual enable bits for the peripheral interrupts.
PIC16F7X 2.2.2.5 PIR1 Register Note: The PIR1 register contains the individual flag bits for the peripheral interrupts. REGISTER 2-5: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt bits are clear prior to enabling an interrupt.
PIC16F7X 2.2.2.6 PIE2 Register The PIE2 register contains the individual enable bits for the CCP2 peripheral interrupt. REGISTER 2-6: PIE2 REGISTER (ADDRESS 8Dh) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — CCP2IE bit 7 bit 0 bit 7-1 Unimplemented: Read as '0' bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Legend: 2.2.2.
PIC16F7X 2.2.2.8 PCON Register Note: The Power Control (PCON) register contains flag bits to allow differentiation between a Power-on Reset (POR), a Brown-out Reset (BOR), a Watchdog Reset (WDT) and an external MCLR Reset. REGISTER 2-8: BOR is unknown on POR. It must be set by the user and checked on subsequent RESETS to see if BOR is clear, indicating a brown-out has occurred.
PIC16F7X 2.3 PCL and PCLATH The program counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any RESET, the upper bits of the PC will be cleared. Figure 2-4 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH).
PIC16F7X 2.5 EXAMPLE 2-2: Indirect Addressing, INDF and FSR Registers MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO CONTINUE : The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself indirectly (FSR = ’0’) will read 00h.
PIC16F7X NOTES: DS30325B-page 28 2002 Microchip Technology Inc.
PIC16F7X 3.0 READING PROGRAM MEMORY The FLASH Program Memory is readable during normal operation over the entire VDD range. It is indirectly addressed through Special Function Registers (SFR). Up to 14-bit numbers can be stored in memory for use as calibration parameters, serial numbers, packed 7-bit ASCII, etc. Executing a program memory location containing data that forms an invalid instruction results in a NOP.
PIC16F7X 3.3 Reading the FLASH Program Memory 3.4 FLASH program memory has its own code protect mechanism. External Read and Write operations by programmers are disabled if this mechanism is enabled. A program memory location may be read by writing two bytes of the address to the PMADR and PMADRH registers and then setting control bit RD (PMCON1<0>). Once the read control bit is set, the microcontroller will use the next two instruction cycles to read the data.
PIC16F7X 4.0 I/O PORTS FIGURE 4-1: Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the PICmicro™ Mid-Range Reference Manual, (DS33023). Data Bus BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS D Q VDD WR Port CK Q P Data Latch N 4.
PIC16F7X TABLE 4-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 bit0 TTL Input/output or analog input. RA1/AN1 bit1 TTL Input/output or analog input. RA2/AN2 bit2 TTL Input/output or analog input. RA3/AN3/VREF bit3 TTL Input/output or analog input or VREF. RA4/T0CKI bit4 ST Input/output or external clock input for Timer0. Output is open drain type. RA5/SS/AN4 bit5 TTL Input/output or slave select input for synchronous serial port or analog input.
PIC16F7X 4.2 PORTB and the TRISB Register PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= ‘1’) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISB bit (= ‘0’) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). Each of the PORTB pins has a weak internal pull-up.
PIC16F7X TABLE 4-3: Name PORTB FUNCTIONS Bit# Buffer (1) Function RB0/INT bit0 TTL/ST Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt-on-change).
PIC16F7X 4.3 FIGURE 4-5: PORTC and the TRISC Register PORTC is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= ‘1’) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISC bit (= ‘0’) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin).
PIC16F7X 4.4 FIGURE 4-6: PORTD and TRISD Registers This section is not applicable to the PIC16F73 or PIC16F76. PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configureable as an input or output. PORTD BLOCK DIAGRAM (IN I/O PORT MODE) Data Bus D WR Port CK Q I/O pin(1) Data Latch PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit PSPMODE (TRISE<4>). In this mode, the input buffers are TTL.
PIC16F7X 4.5 PORTE and TRISE Register This section is not applicable to the PIC16F73 or PIC16F76. PORTE has three pins, RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7, which are individually configureable as inputs or outputs. These pins have Schmitt Trigger input buffers. I/O PORTE becomes control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) is set. In this mode, the user must make sure that the TRISE<2:0> bits are set (pins are configured as digital inputs).
PIC16F7X REGISTER 4-1: TRISE REGISTER (ADDRESS 89h) R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — Bit2 Bit1 Bit0 bit 7 bit 0 bit 7 Parallel Slave Port Status/Control bits: IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overf
PIC16F7X TABLE 4-9: Name PORTE FUNCTIONS Bit# Buffer Type (1) Function Input/output port pin or read control input in Parallel Slave Port mode or analog input. For RD (PSP mode): 1 = IDLE 0 = Read operation. Contents of PORTD register output to PORTD I/O pins (if chip selected). RE0/RD/AN5 bit0 ST/TTL RE1/WR/AN6 bit1 ST/TTL(1) Input/output port pin or write control input in Parallel Slave Port mode or analog input. For WR (PSP mode): 1 = IDLE 0 = Write operation.
PIC16F7X 4.6 Parallel Slave Port The Parallel Slave Port (PSP) is not implemented on the PIC16F73 or PIC16F76. PORTD operates as an 8-bit wide Parallel Slave Port, or Microprocessor Port, when control bit PSPMODE (TRISE<4>) is set. In Slave mode, it is asynchronously readable and writable by an external system using the read control input pin RE0/RD, the write control input pin RE1/WR, and the chip select control input pin RE2/CS. The PSP can directly interface to an 8-bit microprocessor data bus.
PIC16F7X FIGURE 4-9: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 4-10: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 4-11: Address REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 08h PORTD 09h PORTE — — 89h TRISE IBF OBF 0Ch PIR1 8Ch PIE1 9Fh ADCON1 Bit 5 Bit 4 Value on: POR, BOR Value on all other RESETS xxx
PIC16F7X NOTES: DS30325B-page 42 2002 Microchip Technology Inc.
PIC16F7X 5.0 TIMER0 MODULE Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In Counter mode, Timer0 will increment, either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 5.2.
PIC16F7X 5.2 Using Timer0 with an External Clock When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI, with the internal phase clocks, is accomplished by sampling the prescaler output on the Q2 and REGISTER 5-1: Q4 cycles of the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2Tosc (and a small RC delay of 20 ns) and low for at least 2Tosc (and a small RC delay of 20 ns).
PIC16F7X 5.3 Prescaler however, these lines must be used to set a temporary value. The final 1:1 value is then set in lines 10 and 11 (highlighted). (Line numbers are included in the example for illustrative purposes only, and are not part of the actual code.) There is only one prescaler available on the microcontroller; it is shared exclusively between the Timer0 module and the Watchdog Timer.
PIC16F7X NOTES: DS30325B-page 46 2002 Microchip Technology Inc.
PIC16F7X 6.0 TIMER1 MODULE The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L), which are readable and writable. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
PIC16F7X 6.1 Timer1 Operation in Timer Mode 6.2 Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is FOSC/4. The synchronize control bit T1SYNC (T1CON<2>) has no effect, since the internal clock is always in sync. FIGURE 6-1: Timer1 Counter Operation Timer1 may operate in Asynchronous or Synchronous mode, depending on the setting of the TMR1CS bit. When Timer1 is being incremented via an external source, increments occur on a rising edge.
PIC16F7X 6.4 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (Section 6.4.1).
PIC16F7X 6.5 TABLE 6-1: Timer1 Oscillator A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for use with a 32 kHz crystal. Table 6-1 shows the capacitor selection for the Timer1 oscillator.
PIC16F7X 7.0 TIMER2 MODULE Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time-base for the PWM mode of the CCP module(s). The TMR2 register is readable and writable, and is cleared on any device RESET. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). 7.
PIC16F7X REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h) U-0 R/W-0 — R/W-0 TOUTPS3 TOUTPS2 R/W-0 TOUTPS1 R/W-0 R/W-0 R/W-0 R/W-0 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale 0010 = 1:3 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 0
PIC16F7X 8.0 CAPTURE/COMPARE/PWM MODULES Each Capture/Compare/PWM (CCP) module contains a 16-bit register which can operate as a: • 16-bit Capture register • 16-bit Compare register • PWM Master/Slave Duty Cycle register Both the CCP1 and CCP2 modules are identical in operation, with the exception being the operation of the special event trigger. Table 8-1 and Table 8-2 show the resources and interactions of the CCP module(s).
PIC16F7X REGISTER 8-1: CCP1CON REGISTER/CCP2CON REGISTER (ADDRESS: 17h/1Dh) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 bit 7-6 Unimplemented: Read as '0' bit 5-4 CCPxX:CCPxY: PWM Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
PIC16F7X 8.3 8.3.4 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as one of the following and is configured by CCPxCON<3:0>: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set.
PIC16F7X 8.4.1 CCP PIN CONFIGURATION 8.4.4 The user must configure the RC2/CCP1 pin as an output by clearing the TRISC<2> bit. Note: 8.4.2 In this mode, an internal hardware trigger is generated, which may be used to initiate an action. Clearing the CCP1CON register will force the RC2/CCP1 compare output latch to the default low level. This is not the PORTC I/O data latch. The special event trigger output of CCP1 resets the TMR1 register pair.
PIC16F7X 8.5 8.5.1 PWM Mode (PWM) In Pulse Width Modulation mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. Figure 8-3 shows a simplified block diagram of the CCP module in PWM mode.
PIC16F7X 8.5.3 SETUP FOR PWM OPERATION 3. The following steps should be taken when configuring the CCP module for PWM operation: 4. 1. 2. 5. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. TABLE 8-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 1.22 kHz Timer Prescale (1, 4, 16) PR2 Value Address 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.
PIC16F7X 9.0 9.1 SYNCHRONOUS SERIAL PORT (SSP) MODULE SSP Module Overview The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC16F7X REGISTER 9-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 SMP: SPI Data Input Sample Phase bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time (Microwire®) SPI Slave mode: SMP must be cleared when SPI is used in Slave mode I2 C mode: This bit must be maintained clear CKE
PIC16F7X REGISTER 9-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit In SPI mode: 1 = A new byte is received while the SSPBUF register is still holding the previ
PIC16F7X FIGURE 9-1: SSP BLOCK DIAGRAM (SPI MODE) Internal Data Bus Read Write SSPBUF reg SSPSR reg RC4/SDI/SDA RC5/SDO Shift Clock bit0 Peripheral OE To enable the serial port, SSP enable bit, SSPEN (SSPCON<5>) must be set. To reset or reconfigure SPI mode, clear bit SSPEN, re-initialize the SSPCON register, and then set bit SSPEN. This configures the SDI, SDO, SCK, and SS pins as serial port pins.
PIC16F7X FIGURE 9-2: SPI MODE TIMING, MASTER MODE SCK (CKP = 0, CKE = 0) SCK (CKP = 0, CKE = 1) SCK (CKP = 1, CKE = 0) SCK (CKP = 1, CKE = 1) bit7 SDO bit6 bit5 bit2 bit3 bit4 bit1 bit0 SDI (SMP = 0) bit7 bit0 SDI (SMP = 1) bit7 bit0 SSPIF FIGURE 9-3: SPI MODE TIMING (SLAVE MODE WITH CKE = 0) SS (optional) SCK (CKP = 0) SCK (CKP = 1) bit6 bit7 SDO bit5 bit2 bit3 bit4 bit1 bit0 SDI (SMP = 0) bit7 bit0 SSPIF FIGURE 9-4: SPI MODE TIMING (SLAVE MODE WITH CKE = 1) SS SCK (CKP =
PIC16F7X TABLE 9-1: Address REGISTERS ASSOCIATED WITH SPI OPERATION Name Bit 7 Bit 6 0Bh,8Bh.
PIC16F7X 9.3 SSP I2 C Operation The SSP module in I2C mode, fully implements all slave functions, except general call support, and provides interrupts on START and STOP bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing. Two pins are used for data transfer. These are the RC3/ SCK/SCL pin, which is the clock (SCL), and the RC4/ SDI/SDA pin, which is the data (SDA).
PIC16F7X 9.3.1.1 Addressing Once the SSP module has been enabled, it waits for a START condition to occur. Following the START condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse.
PIC16F7X I 2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) FIGURE 9-6: Receiving Address SCL R/W=0 A7 A6 A5 A4 A3 A2 A1 SDA 1 S 2 3 4 5 6 7 ACK Receiving Data Receiving Data ACK ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 9 1 8 2 SSPIF (PIR1<3>) 3 4 5 6 7 8 9 1 2 3 5 4 8 7 6 9 Cleared in software BF (SSPSTAT<0>) P Bus Master terminates transfer SSPBUF register is read SSPOV (SSPCON<6>) Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent.
PIC16F7X 9.3.2 MASTER MODE 9.3.3 Master mode of operation is supported in firmware using interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a RESET or when the SSP module is disabled. The STOP (P) and START (S) bits will toggle based on the START and STOP conditions. Control of the I 2C bus may be taken when the P bit is set, or the bus is IDLE and both the S and P bits are clear.
PIC16F7X 10.0 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) The USART can be configured in the following modes: • Asynchronous (full duplex) • Synchronous - Master (half duplex) • Synchronous - Slave (half duplex) The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI.
PIC16F7X REGISTER 10-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h) R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 R-0 R-x SPEN RX9 SREN CREN — FERR OERR RX9D bit 7 bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins) 0 = Serial port disabled bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous m
PIC16F7X 10.1 USART Baud Rate Generator (BRG) It may be advantageous to use the high baud rate (BRGH = 1), even for slower baud clocks. This is because the FOSC/(16(X + 1)) equation can reduce the baud rate error in some cases. The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTA<2>) also controls the baud rate.
PIC16F7X TABLE 10-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) FOSC = 20 MHz BAUD RATE FOSC = 16 MHz BAUD % ERROR SPBRG VALUE (DECIMAL) 1200 1,221 1.73% 2400 2,404 0.16% 9600 9,470 19,200 38,400 57,600 FOSC = 10 MHz BAUD % ERROR SPBRG VALUE (DECIMAL) BAUD % ERROR SPBRG VALUE (DECIMAL) 255 1,202 0.16% 129 2,404 0.16% 207 1,202 0.16% 129 103 2,404 0.16% -1.36% 32 9,615 64 0.16% 25 9,766 1.73% 15 19,531 1.73% 15 39,063 1.73% 7 19,231 0.16% 12 19,531 1.
PIC16F7X 10.2 USART Asynchronous Mode are set. The TXIF interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit TRMT (TXSTA<1>) shows the status of the TSR register.
PIC16F7X Steps to follow when setting up an Asynchronous Transmission: 5. 1. 6. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH (Section 10.1). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set transmit bit TX9. 2. 3. 4. FIGURE 10-2: Enable the transmission by setting bit TXEN, which will also set bit TXIF.
PIC16F7X 10.2.2 USART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 10-4. The data is received on the RC7/RX/DT pin and drives the data recovery block. The data recovery block is actually a high speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate, or at FOSC. Once Asynchronous mode is selected, reception is enabled by setting bit CREN (RCSTA<4>). The heart of the receiver is the receive (serial) shift register (RSR).
PIC16F7X FIGURE 10-5: ASYNCHRONOUS RECEPTION START bit bit0 RX (pin) bit1 bit7/8 STOP bit Rcv Shift Reg Rcv Buffer Reg START bit0 bit bit7/8 STOP bit bit7/8 STOP bit Word 2 RCREG Word 1 RCREG Read Rcv Buffer reg RCREG START bit RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. An overrun error indicates an error in user firmware. 6.
PIC16F7X 10.3 USART Synchronous Master Mode In Synchronous Master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition, enable bit SPEN (RCSTA<7>) is set in order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and DT (data) lines, respectively.
PIC16F7X FIGURE 10-6: SYNCHRONOUS TRANSMISSION Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4 RC7/RX/DT pin bit 0 bit 1 Word 1 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 RC6/TX/CK pin Write to TXREG reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMTTRMT bit TXEN bit ’1’ ’1’ Note: Sync Master mode; SPBRG = ’0’. Continuous transmission of two 8-bit words.
PIC16F7X 10.3.2 USART SYNCHRONOUS MASTER RECEPTION receive data. Reading the RCREG register will load bit RX9D with a new value, therefore, it is essential for the user to read the RCSTA register before reading RCREG, in order not to lose the old RX9D information. Once synchronous mode is selected, reception is enabled by setting either enable bit SREN (RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is sampled on the RC7/RX/DT pin on the falling edge of the clock.
PIC16F7X TABLE 10-8: Address REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Name 0Bh, 8Bh, INTCON 10Bh,18Bh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 SPEN RX9 SREN CREN — FERR OERR 0Ch PIR1 18h RCSTA 1Ah RCREG USART Receive Register 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE
PIC16F7X TABLE 10-9: Address REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Name 0Bh, 8Bh, INTCON 10Bh,18Bh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 SPEN RX9 SREN CREN ADDEN 0000 000x 0000 000x 0000 0000 0000 0000 CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0Ch PIR1 18h RC
PIC16F7X NOTES: DS30325B-page 82 2002 Microchip Technology Inc.
PIC16F7X 11.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The A/D module has three registers. These registers are: • A/D Result Register ((ADRES) • A/D Control Register 0 (ADCON0) • A/D Control Register 1 ((ADCON1) The 8-bit analog-to-digital (A/D) converter module has five inputs for the PIC16F73/76 and eight for the PIC16F74/77. The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number.
PIC16F7X REGISTER 11-2: ADCON1 REGISTER (ADDRESS 9Fh) U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7-3 Unimplemented: Read as '0' bit 2-0 PCFG2:PCFG0: A/D Port Configuration Control bits PCFG2:PCFG0 RA0 RA1 RA2 RA5 RA3 000 001 010 011 100 101 11x A A A A A A D A A A A A A D A A A A D D D A A A A D D D A VREF A VREF A VREF D RE0(1) RE1(1) RE2(1) A A D D D D D A A D D D D D A A D D D D D VREF VDD RA3 VDD RA3 VDD RA3 VDD A = Analog inpu
PIC16F7X The following steps should be followed for doing an A/D conversion: 4. 1. 5. 2. 3. Configure the A/D module: • Configure analog pins, voltage reference, and digital I/O (ADCON1) • Select A/D conversion clock (ADCON0) • Turn on A/D module (ADCON0) Configure the A/D interrupt (if desired): • Clear ADIF bit • Set ADIE bit • Set PEIE bit • Set GIE bit Select an A/D input channel (ADCON0). FIGURE 11-1: 6. Wait for at least an appropriate acquisition period.
PIC16F7X 11.1 A/D Acquisition Requirements The maximum recommended impedance for analog sources is 10 kΩ. After the analog input channel is selected (changed), the acquisition period must pass before the conversion can be started. For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 11-2.
PIC16F7X 11.2 Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as TAD. The A/D conversion requires 9.0 TAD per 8-bit conversion. The source of the A/D conversion clock is software selectable. The four possible options for TAD are: • • • • 2 TOSC (FOSC/2) 8 TOSC (FOSC/8) 32 TOSC (FOSC/32) Internal RC oscillator (2-6 µs) For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time as small as possible, but no less than 1.6 µs. 11.
PIC16F7X 11.7 Use of the CCP Trigger with minimal software overhead (moving the ADRES to the desired location). The appropriate analog input channel must be selected and an appropriate acquisition time should pass before the “special event trigger” sets the GO/DONE bit (starts a conversion). An A/D conversion can be started by the “special event trigger” of the CCP2 module. This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as 1011 and that the A/D module is enabled (ADON bit is set).
PIC16F7X 12.0 SPECIAL FEATURES OF THE CPU These devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection.
PIC16F7X REGISTER 12-1: U-0 — bit13 bit 13-7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1-0 CONFIGURATION WORD (ADDRESS 2007h)(1) U-0 U-0 U-0 U-0 U-0 U-0 R/P-1 U-0 — — — — — — BOREN — R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 CP0 PWRTEN WDTEN FOSC1 FOSC0 bit0 Unimplemented: Read as ‘1’ BOREN: Brown-out Reset Enable bit 1 = BOR enabled 0 = BOR disabled Unimplemented: Read as ‘1’ CP0: FLASH Program Memory Code Protection bit 1 = Code protection off 0 = All memory locations code protected PWRTEN: Power-
PIC16F7X 12.2 FIGURE 12-2: Oscillator Configurations 12.2.1 OSCILLATOR TYPES The PIC16F7X can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: • • • • LP XT HS RC EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor 12.2.
PIC16F7X TABLE 12-2: Osc Type LP XT HS CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR (FOR DESIGN GUIDANCE ONLY) Crystal Freq Typical Capacitor Values Tested: C1 C2 32 kHz 33 pF 33 pF 200 kHz 15 pF 15 pF 200 kHz 56 pF 56 pF 1 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF 8 MHz 15 pF 15 pF 20 MHz 15 pF 15 pF Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation.
PIC16F7X 12.3 RESET The PIC16F7X differentiates between various kinds of RESET: • • • • • • Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset (during normal operation) WDT Wake-up (during SLEEP) Brown-out Reset (BOR) Some registers are not affected in any RESET condition. Their status is unknown on POR and unchanged in any other RESET.
PIC16F7X 12.4 MCLR 12.6 PIC16F7X devices have a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. The behavior of the ESD protection on the MCLR pin has been altered from previous devices of this family. Voltages applied to the pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event.
PIC16F7X 12.10 Power Control/Status Register (PCON) if bit BOR cleared, indicating a Brown-out Reset occurred. When the Brown-out Reset is disabled, the state of the BOR bit is unpredictable. The Power Control/Status Register, PCON, has two bits to indicate the type of RESET that last occurred. Bit1 is POR (Power-on Reset Status bit). It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset. Bit0 is Brown-out Reset Status bit, BOR.
PIC16F7X TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Devices Power-on Reset, Brown-out Reset MCLR Reset, WDT Reset Wake-up via WDT or Interrupt W INDF TMR0 73 73 73 74 74 74 76 76 76 77 77 77 xxxx xxxx N/A xxxx xxxx uuuu uuuu N/A uuuu uuuu uuuu uuuu N/A uuuu uuuu PCL 73 74 76 77 0000h 0000h PC + 1(2) STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH 73 73 73 73 73 73 73 73 74 74 74 74 74 74 74 74 76 76 76 76 76 76 76 76 77 77 77 77 77 77 77 77 0001 xxxx --0x xx
PIC16F7X TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Devices MCLR Reset, WDT Reset Power-on Reset, Brown-out Reset Wake-up via WDT or Interrupt PIE2 73 74 76 77 ---- ---0 ---- ---0 ---- ---u PCON 73 74 76 77 ---- --qq ---- --uu ---- --uu PR2 73 74 76 77 1111 1111 1111 1111 1111 1111 SSPSTAT 73 74 76 77 --00 0000 --00 0000 --uu uuuu SSPADD 73 74 76 77 0000 0000 0000 0000 uuuu uuuu TXSTA 73 74 76 77 0000 -010 0000 -010 uuuu -uuu SPBRG 73 74 76 77 0000 0000 0000 0000 uuu
PIC16F7X FIGURE 12-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 12-8: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 12-9: SLOW RISE TIME (MCLR TIED TO VDD THROUGH RC NETWORK) 5V VDD 1V 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS30325B-page 98 2002 Microchip
PIC16F7X 12.11 Interrupts The PIC16F7X family has up to 12 sources of interrupt. The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit. A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts.
PIC16F7X 12.11.1 INT INTERRUPT 12.12 Context Saving During Interrupts External interrupt on the RB0/INT pin is edge triggered, either rising, if bit INTEDG (OPTION_REG<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt.
PIC16F7X 12.13 Watchdog Timer (WDT) WDT time-out period values may be found in the Electrical Specifications section under parameter #31. Values for the WDT prescaler (actually a postscaler, but shared with the Timer0 prescaler) may be assigned using the OPTION_REG register. The Watchdog Timer is a free running on-chip RC oscillator, which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin.
PIC16F7X 12.14 Power-down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low, or hi-impedance).
PIC16F7X FIGURE 12-12: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF Flag (INTCON<1>) Interrupt Latency (Note 2) GIE bit (INTCON<7>) Processor in SLEEP INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: PC Inst(PC) = SLEEP Inst(PC - 1) PC+1 PC+2 PC + 2 PC+2 Inst(PC + 1) Inst(PC + 2) SLEEP Inst(PC + 1) Dummy cycle 0004h 0005h Inst(0004h) Inst(0005h) Dummy c
PIC16F7X NOTES: DS30325B-page 104 2002 Microchip Technology Inc.
PIC16F7X 13.0 INSTRUCTION SET SUMMARY The PIC16 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction.
PIC16F7X TABLE 13-2: PIC16F7X INSTRUCTION SET Mnemonic, Operands 14-Bit Opcode Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to
PIC16F7X 13.2 Instruction Descriptions ADDLW Add Literal and W BCF Bit Clear f Syntax: [ label ] ADDLW Syntax: [ label ] BCF Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: (W) + k → (W) Status Affected: C, DC, Z Operation: 0 → (f) Description: The contents of the W register are added to the eight-bit literal ’k’ and the result is placed in the W register. Status Affected: None Description: Bit 'b' in register 'f' is cleared.
PIC16F7X CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 ≤ k ≤ 2047 Operands: None Operation: (PC)+ 1→ TOS, k → PC<10:0>, (PCLATH<4:3>) → PC<12:11> Operation: Status Affected: None 00h → WDT 0 → WDT prescaler, 1 → TO 1 → PD Description: Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH.
PIC16F7X DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - 1 → (destination); skip if result = 0 Operation: (f) + 1 → (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ’f’ are decremented. If ’d’ is 0, the result is placed in the W register.
PIC16F7X MOVF Move f Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: No operation Operation: (f) → (destination) Status Affected: None Status Affected: Z Description: No operation. Description: The contents of register f are moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register, since status flag Z is affected.
PIC16F7X RLF Rotate Left f through Carry SLEEP Syntax: [ label ] RLF Syntax: [ label ] SLEEP Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: None Operation: Operation: See description below Status Affected: C Description: The contents of register ’f’ are rotated one bit to the left through the Carry Flag. If ’d’ is 0, the result is placed in the W register. If ’d’ is 1, the result is stored back in register ’f’.
PIC16F7X SWAPF Swap Nibbles in f XORWF Exclusive OR W with f Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORWF Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f<3:0>) → (destination<7:4>), (f<7:4>) → (destination<3:0>) Operation: (W) .XOR. (f) → (destination) Status Affected: Z Status Affected: None Description: Description: The upper and lower nibbles of register ’f’ are exchanged. If ’d’ is 0, the result is placed in the W register.
PIC16F7X 14.
PIC16F7X 14.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can also link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for precompiled code to be used with the MPLINK object linker.
PIC16F7X 14.8 MPLAB ICD In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD, is a powerful, low cost, run-time development tool. This tool is based on the FLASH PICmicro MCUs and can be used to develop for this and other PICmicro microcontrollers. The MPLAB ICD utilizes the in-circuit debugging capability built into the FLASH devices.
PIC16F7X 14.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board The PICDEM 3 demonstration board is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Module. All the necessary hardware and software is included to run the basic demonstration programs.
Software Tools Programmers Debugger Emulators 9 9 9 9 9 9 PIC17C7XX 9 9 9 9 9 9 PIC17C4X 9 9 9 9 9 9 PIC16C9XX 9 9 9 9 9 PIC16F8XX 9 9 9 9 9 PIC16C8X 9 9 9 9 9 9 PIC16C7XX 9 9 9 9 9 9 PIC16C7X 9 9 9 9 9 9 PIC16F62X 9 9 9 PIC16CXXX 9 9 9 9 PIC16C6X 9 9 9 9 PIC16C5X 9 9 9 9 PIC14000 9 9 9 PIC12CXXX 9 9 9 2002 Microchip Technology Inc. 9 9 9 9 9 9 9 9 9 9 9 9 MCRFXXX 9 9 9 9 9 9 9 9 9 MCP2510 9 * Contact the Microchip Technology Inc. web site at www.microchip.
PIC16F7X NOTES: DS30325B-page 118 2002 Microchip Technology Inc.
PIC16F7X 15.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Ambient temperature under bias................................................................................................................ .-55 to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4) ......................................... -0.
PIC16F7X FIGURE 15-1: PIC16F7X VOLTAGE-FREQUENCY GRAPH 6.0V 5.5V 5.0V Voltage 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 16 MHz 20 MHz Frequency FIGURE 15-2: PIC16LF7X VOLTAGE-FREQUENCY GRAPH 6.0V 5.5V Voltage 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 4 MHz 10 MHz Frequency FMAX = (12 MHz/V) (VDDAPPMIN - 2.5V) + 4 MHz Note 1: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application. Note 2: FMAX has a maximum frequency of 10 MHz. DS30325B-page 120 2002 Microchip Technology Inc.
PIC16F7X 15.1 DC Characteristics: PIC16F73/74/76/77 (Industrial, Extended) PIC16LF73/74/76/77 (Industrial) PIC16LF73/74/76/77 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F73/74/76/77 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F7X 15.1 DC Characteristics: PIC16F73/74/76/77 (Industrial, Extended) PIC16LF73/74/76/77 (Industrial) (Continued) PIC16LF73/74/76/77 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F73/74/76/77 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F7X 15.2 DC Characteristics: PIC16F73/74/76/77 (Industrial, Extended) PIC16LF73/74/76/77 (Industrial) DC CHARACTERISTICS Param Sym No. VIL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Operating voltage VDD range as described in DC Specification, Section 15.1. Min Typ† Max Units Conditions with TTL buffer VSS — 0.15VDD V For entire VDD range VSS — 0.8V V 4.5V ≤ VDD ≤ 5.
PIC16F7X 15.2 DC Characteristics: PIC16F73/74/76/77 (Industrial, Extended) PIC16LF73/74/76/77 (Industrial) (Continued) DC CHARACTERISTICS Param Sym No. VOL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Operating voltage VDD range as described in DC Specification, Section 15.1. Min Typ† Max Units Conditions Output Low Voltage D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.
PIC16F7X 15.3 Timing Parameter Symbology The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
PIC16F7X FIGURE 15-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 15-1: Parameter No. EXTERNAL CLOCK TIMING REQUIREMENTS Symbol FOSC Characteristic External CLKIN Frequency (Note 1) Oscillator Frequency (Note 1) 1 TOSC External CLKIN Period (Note 1) Oscillator Period (Note 1) 2 TCY 3 TosL, TosH 4 † Instruction Cycle Time (Note 1) External Clock in (OSC1) High or Low Time Min Typ† Max Units DC DC DC DC 0.
PIC16F7X FIGURE 15-5: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 14 19 12 18 16 I/O Pin (Input) 15 17 I/O Pin (Output) New Value Old Value 20, 21 Note: Refer to Figure 15-3 for load conditions. TABLE 15-2: Param No.
PIC16F7X FIGURE 15-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer Reset 31 34 34 I/O Pins Note: Refer to Figure 15-3 for load conditions. FIGURE 15-7: BROWN-OUT RESET TIMING VBOR VDD 35 TABLE 15-3: Parameter No.
PIC16F7X FIGURE 15-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 15-3 for load conditions. TABLE 15-4: Param No.
PIC16F7X FIGURE 15-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 15-3 for load conditions. TABLE 15-5: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Param Symbol No. 50* TccL 51* TccH CCP1 and CCP2 input low time CCP1 and CCP2 input high time Characteristic Min No Prescaler 0.
PIC16F7X FIGURE 15-10: PARALLEL SLAVE PORT TIMING (PIC16F74/77 DEVICES ONLY) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 15-3 for load conditions. TABLE 15-6: PARALLEL SLAVE PORT REQUIREMENTS (PIC16F74/77 DEVICES ONLY) Parameter Symbol No.
PIC16F7X FIGURE 15-11: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 Bit6 - - - - - -1 MSb SDO LSb 75, 76 SDI MSb In Bit6 - - - -1 LSb In 74 73 Note: Refer to Figure 15-3 for load conditions. FIGURE 15-12: SPI MASTER MODE TIMING (CKE = 1, SMP = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb Bit6 - - - - - -1 LSb Bit6 - - - -1 LSb In 75, 76 SDI MSb In 74 Note: Refer to Figure 15-3 for load conditions.
PIC16F7X FIGURE 15-13: SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO LSb Bit6 - - - - - -1 77 75, 76 SDI MSb In Bit6 - - - -1 LSb In 74 73 Note: Refer to Figure 15-3 for load conditions. FIGURE 15-14: SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 MSb SDO Bit6 - - - - - -1 LSb 75, 76 SDI MSb In 77 Bit6 - - - -1 LSb In 74 Note: Refer to Figure 15-3 for load conditions.
PIC16F7X TABLE 15-7: Param No.
PIC16F7X TABLE 15-8: Param No.
PIC16F7X TABLE 15-9: Param. No. 100* I2C BUS DATA REQUIREMENTS Symbol THIGH Characteristic Clock high time Min Max Units 100 kHz mode 4.0 — µs Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — µs Device must operate at a minimum of 10 MHz 1.5TCY — 100 kHz mode 4.7 — µs Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — µs Device must operate at a minimum of 10 MHz 1.
PIC16F7X FIGURE 15-17: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure 15-3 for load conditions. TABLE 15-10: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No.
PIC16F7X TABLE 15-12: A/D CONVERTER CHARACTERISTICS: PIC16F7X (INDUSTRIAL, EXTENDED) PIC16LF7X (INDUSTRIAL) Param No. A01 Sym NR Characteristic Resolution Min Typ† Max Units Conditions PIC16F7X — — 8 bits bit VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF PIC16LF7X — — 8 bits bit VREF = VDD = 2.2V A02 EABS Total absolute error — — < ±1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A03 EIL Integral linearity error — — < ±1 LSb VREF = VDD = 5.
PIC16F7X FIGURE 15-19: A/D CONVERSION TIMING BSF ADCON0, GO 134 1 TCY (TOSC/2)(1) 131 Q4 130 A/D CLK 132 7 A/D DATA 6 5 4 3 2 1 0 NEW_DATA OLD_DATA ADRES ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 15-13: A/D CONVERSION REQUIREMENTS Param Sym No. 130 TAD Characteristic A/D clock period Min Typ† Max Units Conditions PIC16F7X 1.
PIC16F7X NOTES: DS30325B-page 140 2002 Microchip Technology Inc.
PIC16F7X 16.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
PIC16F7X FIGURE 16-3: TYPICAL IDD vs. FOSC OVER VDD (XT MODE) 0.9 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 0.8 5.5V 0.7 5.0V 0.6 IDD (mA) 4.5V 0.5 4.0V 3.5V 0.4 3.0V 0.3 2.5V 2.0V 0.2 0.1 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 3.5 4.0 FOSC (MHz) FIGURE 16-4: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE) 1.2 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 1.0 5.
PIC16F7X FIGURE 16-5: TYPICAL IDD vs. FOSC OVER VDD (LP MODE) 55 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) IDD (µA) 50 45 5.5V 40 5.0V 35 4.5V 4.0V 30 3.5V 25 3.0V 20 2.5V 2.0V 15 10 30 40 50 60 70 80 90 80 90 100 FOSC (kHz) FIGURE 16-6: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE) 100 90 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 5.5V 80 5.
PIC16F7X FIGURE 16-7: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 20 pF, 25°C) 5.0 4.5 Operation above 4 MHz is not recomended 4.0 3.5 10 kΩ Freq (MHz) 3.0 2.5 2.0 1.5 1.0 100 kΩ 0.5 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-8: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 100 pF, 25°C) 5.0 Operation above 4 MHz is not recomended 4.0 5.1 kΩ Freq (MHz) 3.0 10 kΩ 2.0 1.0 100 kΩ 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16F7X FIGURE 16-9: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 300 pF, 25°C) 300 250 3.3 kΩ 200 Freq (kHz) 5.1 kΩ 150 10 kΩ 100 50 100 kΩ 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-10: IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) 100 Max 125°C 10 IPD (uA) Max 85°C 1 Typ 25°C 0.1 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 0.01 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16F7X FIGURE 16-11: ∆IBOR vs. VDD OVER TEMPERATURE 1,000 Max (125˚C) Typ (25˚C) Device in SLEEP Indeterminant State IDD (µA) Device in RESET 100 Note: Device current in RESET depends on Oscillator mode, frequency and circuit. Max (125˚C) Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) Typ (25˚C) 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.0 5.5 VDD (V) FIGURE 16-12: TYPICAL AND MAXIMUM ∆IWDT vs.
PIC16F7X FIGURE 16-13: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40°C TO 125°C) 50 45 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 40 35 WDT Period (ms) Max (125°C) 30 25 Typ (25°C) 20 Min (-40°C) 15 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-14: AVERAGE WDT PERIOD vs.
PIC16F7X FIGURE 16-15: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40°C TO 125°C) 5.5 5.0 4.5 4.0 Max 3.5 VOH (V) Typ (25°C) 3.0 2.5 Min 2.0 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 1.5 1.0 0.5 0.0 0 5 10 15 20 25 IOH (-mA) FIGURE 16-16: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40°C TO 125°C) 3.5 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 3.0 2.
PIC16F7X FIGURE 16-17: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 5V, -40°C TO 125°C) 1.0 0.9 Max (125°C) Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 0.8 0.7 Max (85°C) VOL (V) 0.6 0.5 Typ (25°C) 0.4 0.3 Min (-40°C) 0.2 0.1 0.0 0 5 10 15 20 25 IOL (-mA) FIGURE 16-18: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 3V, -40°C TO 125°C) 3.
PIC16F7X FIGURE 16-19: MINIMUM AND MAXIMUM VIN vs. VDD, (TTL INPUT, -40°C TO 125°C) 1.5 1.4 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 1.3 VTH Max (-40°C) 1.2 1.1 VIN (V) VTH Typ (25°C) 1.0 VTH Min (125°C) 0.9 0.8 0.7 0.6 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-20: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40°C TO 125°C) 4.
PIC16F7X 17.0 PACKAGING INFORMATION 17.1 Package Marking Information 28-Lead PDIP (Skinny DIP) Example PIC16F77-I/SP XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC 0210017 Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SSOP 28-Lead MLF PIC16F73 -I/SS 0210017 Example 1 1 XXXXXXXX XXXXXXXX YYWWNNN PIC16F73 -I/ML 0210017 Legend: * 0210017 Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Note: PIC16F76-I/SO XX...
PIC16F7X Package Marking Information (Cont’d) 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead PLCC XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS30325B-page 152 PIC16F77-I/P 0210017 Example PIC16F77 -I/PT 0210017 Example PIC16F77 -I/L 0210017 2002 Microchip Technology Inc.
PIC16F7X 17.2 Package Details The following sections give the technical details of the packages. 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c β B1 A1 eB Units Number of Pins Pitch p B Dimension Limits n p INCHES* MIN NOM MILLIMETERS MAX MIN NOM 28 MAX 28 .100 2.54 Top to Seating Plane A .140 .150 .160 3.56 3.81 4.06 Molded Package Thickness A2 .125 .130 .135 3.18 3.30 3.43 8.26 Base to Seating Plane A1 .
PIC16F7X 28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) E E1 p D B 2 1 n h α 45° c A2 A φ β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Top Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L φ c B α β A1 MIN .093 .088 .004 .394 .288 .695 .010 .
PIC16F7X 28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP) E E1 p D B 2 1 n α A c A2 φ A1 L β Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L c φ B α β MIN .068 .064 .002 .299 .201 .396 .022 .004 0 .
PIC16F7X 28-Lead Plastic Micro Leadframe Package (MF) 6x6 mm Body (MLF) EXPOSED METAL PADS E E1 Q D1 D D2 p 2 1 B n R E2 CH x 45 L TOP VIEW BOTTOM VIEW α A2 A A1 A3 Units Dimension Limits Number of Pins INCHES MIN n MILLIMETERS* NOM MAX MIN MAX NOM 28 28 Pitch p Overall Height A .033 .039 0.85 1.00 Molded Package Thickness A2 .026 .031 0.65 0.80 Standoff A1 .0004 .002 0.01 0.05 Base Thickness A3 .008 REF. 0.20 REF. 6.00 BSC .026 BSC .000 E .
PIC16F7X 28-Lead Plastic Micro Leadframe Package (MF) 6x6 mm Body (MLF) (Continued) M B L M p PACKAGE EDGE SOLDER MASK Units Pitch Dimension Limits p INCHES MIN NOM MILLIMETERS* MAX MIN .026 BSC NOM MAX 0.65 BSC Pad Width B .009 .011 .014 0.23 0.28 Pad Length L .020 .024 .030 0.50 0.60 Pad to Solder Mask M .005 .006 0.13 0.35 0.75 0.15 *Controlling Parameter Drawing No. C04-2114 2002 Microchip Technology Inc.
PIC16F7X 40-Lead Plastic Dual In-line (P) – 600 mil (PDIP) E1 D α 2 1 n E A2 A L c β B1 A1 eB p B Units Dimension Limits n p MIN INCHES* NOM 40 .100 .175 .150 MAX MILLIMETERS NOM 40 2.54 4.06 4.45 3.56 3.81 0.38 15.11 15.24 13.46 13.84 51.94 52.26 3.05 3.30 0.20 0.29 0.76 1.27 0.36 0.46 15.75 16.51 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .160 .190 Molded Package Thickness A2 .140 .160 Base to Seating Plane .015 A1 Shoulder to Shoulder Width E .595 .600 .
PIC16F7X 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.
PIC16F7X 44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC) E E1 #leads=n1 D1 D n 1 2 CH2 x 45 ° CH1 x 45 ° α A3 A2 35° A B1 B c β E2 Units Dimension Limits n p A1 p D2 INCHES* NOM 44 .050 11 .165 .173 .145 .153 .020 .028 .024 .029 .040 .045 .000 .005 .685 .690 .685 .690 .650 .653 .650 .653 .590 .620 .590 .620 .008 .011 .026 .029 .013 .020 0 5 0 5 MIN MAX MILLIMETERS NOM 44 1.27 11 4.19 4.39 3.68 3.87 0.51 0.71 0.61 0.74 1.02 1.14 0.00 0.13 17.40 17.53 17.40 17.53 16.51 16.59 16.51 16.
PIC16F7X APPENDIX A: REVISION HISTORY Version Date Revision Description A 2000 This is a new data sheet. However, these devices are similar to the PIC16C7X devices found in the PIC16C7X Data Sheet (DS30390) or the PIC16F87X devices (DS30292). B 2001 Final data sheet. Includes device characterization data. Addition of extended temperature devices. Addition of 28-pin MLF package. Minor typographic revisions throughout.
PIC16F7X APPENDIX C: CONVERSION CONSIDERATIONS Considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in Table C-1.
PIC16F7X INDEX A A/D A/D Conversion Status (GO/DONE Bit) ..................... 83 Acquisition Requirements .......................................... 86 ADCON0 Register ..................................................... 83 ADCON1 Register ..................................................... 83 ADRES Register ........................................................ 83 Analog Port Pins ...................................... 8, 10, 12, 39 Analog-to-Digital Converter .......................................
PIC16F7X Code Protection ........................................................ 89, 103 Computed GOTO ............................................................... 26 Configuration Bits .............................................................. 89 Continuous Receive Enable (CREN Bit) ............................ 70 Conversion Considerations .............................................. 162 D D/A bit ................................................................................ 60 Data Memory ...
PIC16F7X M Master Clear (MCLR) .................................................... 8, 10 MCLR Reset, Normal Operation ...................93, 95, 96 MCLR Reset, SLEEP ...................................93, 95, 96 Operation and ESD Protection .................................. 94 MCLR/VPP Pin ..................................................................... 8 MCLR/VPP Pin ................................................................... 10 Memory Organization ...........................................
PIC16F7X PORTE Register ................................................................ 37 Postscaler, WDT Assignment (PSA bit) ................................................. 20 Rate Select (PS2:PS0 bits) ........................................ 20 Power-down Mode. See SLEEP Power-on Reset (POR) .................................. 89, 93, 95, 96 Oscillator Start-up Timer (OST) .......................... 89, 94 POR Status (POR bit) ................................................
PIC16F7X S S (START) bit .................................................................... 60 SCI. See USART SCL .................................................................................... 65 Serial Communication Interface. See USART SLEEP ................................................................89, 93, 102 SMP bit .............................................................................. 60 Software Simulator (MPLAB SIM) ...................................
PIC16F7X USART Synchronous Transmission (Through TXEN) ........................................ 78 Wake-up from SLEEP via Interrupt .......................... 103 Watchdog Timer ...................................................... 128 Timing Parameter Symbology ......................................... 125 Timing Requirements Capture/Compare/PWM (CCP1 and CCP2) ............ 130 CLKOUT and I/O ..................................................... 127 External Clock .........................................
PIC16F7X ON-LINE SUPPORT Systems Information and Upgrade Hot Line Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.
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PIC16F7X PIC16F7X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX XXX Package Pattern Examples: a) b) Device PIC16F7X(1), PIC16F7XT(1); VDD range 4.0V to 5.5V PIC16LF7X(1), PIC16LF7XT(1); VDD range 2.0V to 5.5V Temperature Range I E = -40°C to +85°C = -40°C to +125°C c) PIC16F77-I/P 301 = Industrial temp., PDIP package, normal VDD limits, QTP pattern #301.
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