Datasheet

PIC16F72X/PIC16LF72X
DS41341E-page 14 © 2009 Microchip Technology Inc.
FIGURE 1-1: PIC16F722/723/726/PIC16LF722/723/726 BLOCK DIAGRAM
13
Data Bus
8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr
7
RAM Addr
9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR
VDD
PORTA
RA4
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
8
8
Brown-out
Reset
AUSART
Timer0
Timer1
Timer2
RA3
RA1
RA0
8
3
Analog-To-Digital Converter
RA6
RA7
RB6
RB7
VSS
T0CKI
T1G
T1CKI
VREF
Synchronous
SDA
SCL
SSSDO
Serial Port
SDI/
SCK/
TX/CK
RX/DT
Internal
Oscillator
Block
Configuration
13
Data Bus
8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr
7
RAM Addr
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
MCLR
VDD
RC1
8
8
Brown-out
Reset
AUSART
Timer0
Timer1
Timer2
8
3
VSS
T0CKI
T1CKI
Synchronous
SDA
SCL
SSSDO
Serial Port
SDI/
SCK/
Internal
Oscillator
Block
Configuration
13
Data Bus
8
14
Program
Bus
Instruction Reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr
7
RAM Addr
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode and
Control
Timing
Generation
MCLR
VDD
PORTB
PORTC
RA5
8
8
Brown-out
Reset
Timer0
Timer1
Timer2
RA2
8
3
RB0
RB1
RB2
RB3
RB4
RB5
VSS
T0CKI
T1CKI
Synchronous
SDA
SCL
SSSDO
Serial Port
SDI/
SCK/
Internal
Oscillator
Block
Configuration
CCP2
CCP2
Timer1
32 kHz
Oscillator
PORTE
RE3
CCP1
CCP1
T1OSI
T1OSO
AN9
AN0 AN1
AN2
AN3 AN4
AN8
AN10 AN11
AN12 AN13
LDO
(1)
Regulator
Flash
Program
Memory
Note 1: PIC16F722/723/726 only.
RAM
Capacitive Sensing Module
CPS6
CPS0 CPS1
CPS2
CPS3 CPS4
CPS5
CPS7