Datasheet

© 2009 Microchip Technology Inc. DS41341E-page 77
PIC16F72X/PIC16LF72X
FIGURE 6-17: BLOCK DIAGRAM OF RC4
FIGURE 6-18: BLOCK DIAGRAM OF RC5
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
RD
WR
WR
RD
Data Bus
PORTC
TRISC
TRISC
PORTC
To SSP SPI
0
1
SSPEN
SSPM = I
2
C™ MODE
SDA FROM SSP
To SSP I
2
C™
I
2
C™
(1)
SDA Input
0
1
1
0
Data Input
(2)
Note 1: I
2
C™ Schmitt Trigger has special input levels.
2: I
2
C™ Slew Rate limiting controlled by SMP bit of SSPSTAT register.
0
1
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
RD
WR
WR
RD
Data Bus
PORTC
TRISC
TRISC
PORTC
SDO
SSPEN
SSPM = SPI MODE
SDO
EN