Datasheet

PIC16F72X/PIC16LF72X

TABLE 3-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS

TABLE 3-6: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS

Condition

Program

Counter

STATUS

PCON

Power-on Reset 0000h 0001 1xxx ---- --0x

MCLR

Reset during normal operation 0000h 000u uuuu ---- --uu

MCLR Reset during Sleep 0000h 0001 0uuu ---- --uu

WDT Reset 0000h 0000 uuuu ---- --uu

WDT Wake-up PC + 1 uuu0 0uuu ---- --uu

Brown-out Reset 0000h 0001 1xxx ---- --10

Interrupt Wake-up from Sleep PC + 1

(1)

uuu1 0uuu ---- --uu

Legend: u = unchanged, x = unknown,

- = unimplemented bit, reads as ‘0’.

Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with

the interrupt vector (0004h) after execution of PC + 1.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Value on

all other

Resets

(1)

STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu

PCON

— — — — — —PORBOR ---- --qq ---- --uu

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are not

used by Resets.

Note 1: Other (non Power-up) Resets include MCLR

Reset and Watchdog Timer Reset during normal operation.