Datasheet

 2010-2012 Microchip Technology Inc. DS41417B-page 225
PIC16(L)F722A/723A
TABLE 23-13: I
2
C™ BUS DATA REQUIREMENTS
Param.
No.
Symbol Characteristic Min. Max. Units Conditions
SP100* T
HIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — s Device must operate at a
minimum of 10 MHz
SSP Module 1.5T
CY —
SP101* T
LOW Clock low time 100 kHz mode 4.7 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 — s Device must operate at a
minimum of 10 MHz
SSP Module 1.5TCY —
SP102* TR SDA and SCL rise
time
100 kHz mode — 1000 ns
400 kHz mode 20 +
0.1C
B
300 ns CB is specified to be from
10-400 pF
SP103* T
F SDA and SCL fall
time
100 kHz mode — 250 ns
400 kHz mode 20 +
0.1C
B
250 ns CB is specified to be from
10-400 pF
SP106* T
HD:DAT Data input hold
time
100 kHz mode 0 — ns
400 kHz mode 0 0.9 s
SP107* T
SU:DAT Data input setup
time
100 kHz mode 250 — ns (Note 2)
400 kHz mode 100 — ns
SP109* T
AA Output valid from
clock
100 kHz mode — 3500 ns (Note 1)
400 kHz mode — — ns
SP110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free
before a new transmis-
sion can start
400 kHz mode 1.3 — s
SP111 CB Bus capacitive loading — 400 pF
* These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A Fast mode (400 kHz) I
2
C™ bus device can be used in a Standard mode (100 kHz) I
2
C bus system, but
the requirement T
SU:DAT 250 ns must then be met. This will automatically be the case if the device does
not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal,
it must output the next data bit to the SDA line T
R max. + TSU:DAT = 1000 + 250 = 1250 ns (according to
the Standard mode I
2
C bus specification), before the SCL line is released.