Datasheet

PIC16(L)F722A/723A
DS41417B-page 168  2010-2012 Microchip Technology Inc.
17.2.5 RECEPTION
When the R/W bit of the received address byte is clear,
the master will write data to the slave. If an address
match occurs, the received address is loaded into the
SSPBUF register. An address byte overflow will occur
if that loaded address is not read from the SSPBUF
before the next complete byte is received.
An SSP interrupt is generated for each data transfer byte.
The BF, R/W
and D/A bits of the SSPSTAT register are
used to determine the status of the last received byte.
FIGURE 17-10: I
2
C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
P
9
8
765
D0
D1
D2
D3
D4
D5D6
D7
S
A7
A6 A5 A4 A3 A2
A1
SDA
SCL
1
2
3456 78
9123
4
567
89
12
34
Bus Master
sends Stop
condition
Bit SSPOV is set because the SSPBUF register is still full.
Cleared in software
SSPBUF register is read
ACK
Receiving Data
Receiving Data
D0
D1
D2
D3D4D5D6
D7
ACK
R/W = 0
Receiving Address
SSPIF
BF
SSPOV
ACK
ACK is not sent.