PIC16(L)F722A/723A Data Sheet 28-Pin Flash Microcontrollers with nanoWatt XLP Technology 2010-2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC16(L)F722A/723A 28-Pin Flash Microcontrollers with nanoWatt XLP Technology Devices Included In This Data Sheet: PIC16F722A/723A Devices: • PIC16F722A • PIC16F723A PIC16LF722A/723A Devices: • PIC16LF722A • PIC16LF723A High-Performance RISC CPU: • Only 35 Instructions to Learn: - All single-cycle instructions except branches • Operating Speed: - DC – 20 MHz oscillator/clock input - DC – 200 ns instruction cycle • Up to 4K x 14 Words of Flash Program Memory • Up to 192 Bytes of Data Memory (RAM) • Interrup
PIC16(L)F722A/723A Device Program Memory Flash (words) PIC16F722A/ 2048 PIC16LF722A PIC16F723A/ 4096 PIC16LF723A Note 1: One pin is input-only. DS41417B-page 4 SRAM (bytes) I/Os(1) Interrupts 8-bit A/D (ch) AUSART CCP Timers 8/16-bit 128 25 12 11 Yes 2 2/1 192 25 12 11 Yes 2 2/1 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A Pin Diagrams – 28-PIN SPDIP/SOIC/SSOP/QFN/UQFN (PIC16(L)F722A/723A) SPDIP, SOIC, SSOP 28 RB7/ICSPDAT 2 27 RB6/ICSPCLK AN1/RA1 3 26 RB5/AN13/CPS5/T1G AN2/RA2 4 25 RB4/AN11/CPS4 VREF/AN3/RA3 5 RB3/AN9/CPS3/CCP2(1) T0CKI/CPS6/RA4 6 24 23 VCAP(3)/SS(2)/CPS7/AN4/RA5 7 VSS 8 CLKIN/OSC1/RA7 9 PIC16LF722A/723A 1 PIC16F722A/723A VPP/MCLR/RE3 VCAP(3)/SS(2)/AN0/RA0 RB2/AN8/CPS2 22 21 RB1/AN10/CPS1 RB0/AN12/CPS0/INT 20 VDD 19 (1) CCP2 /T1OSI/RC1 12 17 RC6/TX/CK
PIC16(L)F722A/723A TABLE 1: 28-PIN SPDIP/SOIC/SSOP/QFN/UQFN SUMMARY (PIC16(L)F722A/723A) I/O 28-Pin SPDIP, SOIC, SSOP 28-Pin QFN, UQFN A/D Cap Sensor Timers CCP AUSART SSP RA0 2 27 AN0 — — — — SS(3) — — VCAP(4) RA1 3 28 AN1 — — — — — — — — RA2 4 1 AN2 — — — — — — — — RA3 5 2 AN3/VREF — — — — — — — — Interrupt Pull-Up Basic RA4 6 3 — CPS6 T0CKI — — — — — — RA5 7 4 AN4 CPS7 — — — SS(3) — — VCAP(4) RA6 10 7 — — — — — —
PIC16(L)F722A/723A Table of Contents 1.0 Device Overview ......................................................................................................................................................................... 9 2.0 Memory Organization ................................................................................................................................................................ 15 3.0 Resets ....................................................................................
PIC16(L)F722A/723A TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
PIC16(L)F722A/723A 1.0 DEVICE OVERVIEW The PIC16(L)F722A/723A devices are covered by this data sheet. They are available in 28-pin packages. Figure 1-1 shows a block diagram of the PIC16(L)F722A/723A devices. Table 1-1 shows the pinout descriptions. 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A FIGURE 1-1: PIC16(L)F722A/723A BLOCK DIAGRAM PORTA Configuration 13 Program Counter Flash Program Memory Program Bus 8 Level Stack (13-bit) 14 RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 8 Data Bus RAM PORTB 9 RAM Addr Addr MUX Instruction Instruction Reg reg 7 Direct Addr 8 Indirect Addr FSR FSR Reg reg STATUS STATUS Reg reg 8 3 Power-up Timer Oscillator Start-up Timer Instruction Decode Decodeand & Control OSC1/CLKIN OSC2/CLKOUT RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 PORTE 8 RE3
PIC16(L)F722A/723A TABLE 1-1: PIC16F722A/723A PINOUT DESCRIPTION Name RA0/AN0/SS/VCAP RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/CPS6/T0CKI RA5/AN4/CPS7/SS/VCAP RA6/OSC2/CLKOUT/VCAP RA7/OSC1/CLKIN RB0/AN12/CPS0/INT RB1/AN10/CPS1 RB2/AN8/CPS2 RB3/AN9/CPS3/CCP2 Function Input Type RA0 TTL AN0 AN Output Type CMOS General purpose I/O. — SS ST — VCAP Power Power RA1 TTL AN1 AN RA2 TTL AN2 AN RA3 TTL AN3 AN VREF AN RA4 TTL Description A/D Channel 0 input. Slave Select input.
PIC16(L)F722A/723A TABLE 1-1: PIC16F722A/723A PINOUT DESCRIPTION (CONTINUED) Name RB4/AN11/CPS4 RB5/AN13/CPS5/T1G RB6/ICSPCLK/ICDCLK RB7/ICSPDAT/ICDDAT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT RE3/MCLR/VPP Function Input Type RB4 TTL Output Type Description CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN11 AN — A/D Channel 11 input. CPS4 AN — Capacitive sensing input 4.
PIC16(L)F722A/723A Note: The PIC16F722A/723A devices have an internal low dropout voltage regulator. An external capacitor must be connected to one of the available VCAP pins to stabilize the regulator. For more information, see Section 5.0 “Low Dropout (LDO) Voltage Regulator”. The PIC16LF722A/723A devices do not have the voltage regulator and therefore no external capacitor is required. 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A NOTES: DS41417B-page 14 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A 2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization The PIC16(L)F722A/723A has a 13-bit program counter capable of addressing a 2K x 14 program memory space for the PIC16(L)F722A (0000h-07FFh) and a 4K x 14 program memory space for the PIC16(L)F723A (0000h-0FFFh). Accessing a location above the memory boundaries for the PIC16(L)F722A will cause a wrap-around within the first 2K x 14 program memory space.
PIC16(L)F722A/723A 2.2 Data Memory Organization The data memory is partitioned into multiple banks which contain the General Purpose Registers (GPRs) and the Special Function Registers (SFRs). Bits RP0 and RP1 are bank select bits. RP1 RP0 0 0 Bank 0 is selected 0 1 Bank 1 is selected 1 0 Bank 2 is selected 1 1 Bank 3 is selected Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers.
PIC16(L)F722A/723A FIGURE 2-3: PIC16(L)F722A SPECIAL FUNCTION REGISTERS File Address Indirect addr.(*) 00h Indirect addr.(*) 80h Indirect addr.(*) 100h Indirect addr.
PIC16(L)F722A/723A FIGURE 2-4: PIC16(L)F723A SPECIAL FUNCTION REGISTERS File Address Indirect addr.(*) 00h Indirect addr.(*) 80h Indirect addr.(*) 100h Indirect addr.
PIC16(L)F722A/723A TABLE 2-1: Address Name PIC16(L)F722A/723A SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Page Bank 0 00h(2) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 26,34 01h TMR0 Timer0 Module Register xxxx xxxx 99,34 02h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 25,34 03h(2) STATUS 0001 1xxx 22,34 IRP RP1 RP0 TO PD Z DC C 0
PIC16(L)F722A/723A TABLE 2-1: Address PIC16(L)F722A/723A SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Page Bank 1 80h(2) INDF 81h OPTION_REG 82h(2) PCL 83h(2) STATUS Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS xxxx xxxx 26,34 PSA PS2 PS1 PS0 1111 1111 23,35 0000 0000 25,34 TO PD Z DC C 0001 1xxx 22,34 T0SE Program Counter (PC)
PIC16(L)F722A/723A TABLE 2-1: Address PIC16(L)F722A/723A SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Page Bank 2 100h(2) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 26,34 101h TMR0 Timer0 Module Register xxxx xxxx 99,34 102h(2) PCL Program Counter’s (PC) Least Significant Byte 0000 0000 25,34 103h(2) STATUS 0001 1xxx 22,34 104h(2) FSR I
PIC16(L)F722A/723A 2.2.2.1 STATUS Register The STATUS register, shown in Register 2-1, contains: • the arithmetic status of the ALU • the Reset status • the bank select bits for data memory (SRAM) The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
PIC16(L)F722A/723A 2.2.2.2 OPTION register Note: The OPTION register, shown in Register 2-2, is a readable and writable register, which contains various control bits to configure: • • • • Timer0/WDT prescaler External RB0/INT interrupt Timer0 Weak pull-ups on PORTB REGISTER 2-2: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting PSA bit of the OPTION register to ‘1’. Refer to Section 12.3 “Timer1 Prescaler”.
PIC16(L)F722A/723A 2.2.2.3 PCON Register The Power Control (PCON) register contains flag bits (refer to Table 3-2) to differentiate between a: • • • • Power-on Reset (POR) Brown-out Reset (BOR) Watchdog Timer Reset (WDT) External MCLR Reset The PCON register also controls the software enable of the BOR. The PCON register bits are shown in Register 2-3.
PIC16(L)F722A/723A 2.3 PCL and PCLATH The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in Figure 2-5 shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH).
PIC16(L)F722A/723A 2.5 Indirect Addressing, INDF and FSR Registers EXAMPLE 2-2: INDIRECT ADDRESSING MOVLW020h ;initialize pointer MOVWFFSR ;to RAM BANKISEL020h NEXTCLRFINDF ;clear INDF register INCFFSR ;inc pointer BTFSSFSR,4 ;all done? GOTONEXT ;no clear next CONTINUE ;yes continue The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register.
PIC16(L)F722A/723A 3.0 RESETS The PIC16(L)F722A/723A various kinds of Reset: a) b) c) d) e) f) differentiates between Power-on Reset (POR) WDT Reset during normal operation WDT Reset during Sleep MCLR Reset during normal operation MCLR Reset during Sleep Brown-out Reset (BOR) A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 3-1. Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset.
PIC16(L)F722A/723A TABLE 3-1: STATUS BITS AND THEIR SIGNIFICANCE POR BOR TO PD 0 x 1 1 Power-on Reset or LDO Reset 0 x 0 x Illegal, TO is set on POR 0 x x 0 Illegal, PD is set on POR 1 0 1 1 Brown-out Reset 1 1 0 1 WDT Reset 1 1 0 0 WDT Wake-up 1 1 u u MCLR Reset during normal operation 1 1 1 0 MCLR Reset during Sleep or interrupt wake-up from Sleep TABLE 3-2: Condition RESET CONDITION FOR SPECIAL REGISTERS(2) Program Counter STATUS Register PCON Register P
PIC16(L)F722A/723A 3.1 MCLR 3.3 The PIC16(L)F722A/723A has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a Reset does not drive the MCLR pin low. Voltages applied to the pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD.
PIC16(L)F722A/723A 3.4.2 WDT CONTROL The WDTE bit is located in the Configuration Word Register 1. When set, the WDT runs continuously. The PSA and PS<2:0> bits of the OPTION register control the WDT period. See Section 11.0 “Timer0 Module” for more information.
PIC16(L)F722A/723A 3.5 Brown-Out Reset (BOR) If VDD falls below VBOR for greater than parameter (TBOR) (see Section 23.0 “Electrical Specifications”), the brown-out situation will reset the device. This will occur regardless of VDD slew rate. A Reset is not ensured to occur if VDD falls below VBOR for more than parameter (TBOR). Brown-out Reset is enabled by programming the BOREN<1:0> bits in the Configuration register.
PIC16(L)F722A/723A 3.6 Time-out Sequence 3.7 On power-up, the time-out sequence is as follows: first, PWRT time-out is invoked after POR has expired, then OST is activated after the PWRT time-out has expired. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit = 1 (PWRT disabled), there will be no time-out at all. Figure 3-4, Figure 3-5 and Figure 3-6 depict time-out sequences.
PIC16(L)F722A/723A FIGURE 3-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2 FIGURE 3-5: VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 3-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD): CASE 3 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A TABLE 3-4: INITIALIZATION CONDITION FOR REGISTERS Register W Address Power-on Reset/ Brown-out Reset(1) MCLR Reset/ WDT Reset Wake-up from Sleep through Interrupt/Time-out — xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h/80h/ 100h/180h xxxx xxxx xxxx xxxx uuuu uuuu TMR0 01h/101h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h/ 102h/182h 0000 0000 0000 0000 PC + 1(3) STATUS 03h/83h/ 103h/183h 0001 1xxx 000q quuu(4) uuuq quuu(4) FSR 04h/84h/ 104h/184h xxxx xxxx uuuu uuuu
PIC16(L)F722A/723A TABLE 3-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED) Register Address Power-on Reset/ Brown-out Reset(1) MCLR Reset/ WDT Reset Wake-up from Sleep through Interrupt/Time-out OPTION_REG 81h/181h 1111 1111 1111 1111 uuuu uuuu TRISA 85h 1111 1111 1111 1111 uuuu uuuu TRISB 86h 1111 1111 1111 1111 uuuu uuuu TRISC 87h 1111 1111 1111 1111 uuuu uuuu TRISE 89h ---- 1--- ---- 1--- ---- u--- PIE1 8Ch 0000 0000 0000 0000 uuuu uuuu PIE2 8Dh ---- ---0 ---
PIC16(L)F722A/723A TABLE 3-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Program Counter STATUS Register PCON Register Power-on Reset 0000h 0001 1xxx ---- --0x MCLR Reset during normal operation 0000h 000u uuuu ---- --uu MCLR Reset during Sleep 0000h 0001 0uuu ---- --uu WDT Reset 0000h 0000 uuuu ---- --uu WDT Wake-up PC + 1 uuu0 0uuu ---- --uu Brown-out Reset 0000h 0001 1xxx ---- --10 uuu1 0uuu ---- --uu Condition Interrupt Wake-up from Sleep PC + 1 (1) Legend: u = unch
PIC16(L)F722A/723A 4.0 INTERRUPTS The PIC16(L)F722A/723A device family features an interruptible core, allowing certain events to preempt normal program flow. An Interrupt Service Routine (ISR) is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode.
PIC16(L)F722A/723A 4.1 Operation interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. Interrupts are disabled upon any device Reset.
PIC16(L)F722A/723A 4.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate interrupt enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction.
PIC16(L)F722A/723A 4.5.1 INTCON REGISTER Note: The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, PORTB change and external RB0/INT/SEG0 pin interrupts. REGISTER 4-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register.
PIC16(L)F722A/723A 4.5.2 PIE1 REGISTER The PIE1 register contains the interrupt enable bits, as shown in Register 4-2. REGISTER 4-2: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
PIC16(L)F722A/723A 4.5.3 PIE2 REGISTER The PIE2 register contains the interrupt enable bits, as shown in Register 4-3. REGISTER 4-3: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
PIC16(L)F722A/723A 4.5.4 PIR1 REGISTER The PIR1 register contains the interrupt flag bits, as shown in Register 4-4. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16(L)F722A/723A 4.5.5 PIR2 REGISTER The PIR2 register contains the interrupt flag bits, as shown in Register 4-5. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16(L)F722A/723A 5.0 LOW DROPOUT (LDO) VOLTAGE REGULATOR The PIC16F722A/723A devices differ from the PIC16LF722A/723A devices due to an internal Low Dropout (LDO) voltage regulator. The PIC16F722A/ 723A contain an internal LDO, while the PIC16LF722A/ 723A do not. The lithography of the die allows a maximum operating voltage of 3.6V on the internal digital logic. In order to continue to support 5.0V designs, a LDO voltage regulator is integrated on the die.
PIC16(L)F722A/723A NOTES: DS41417B-page 46 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A 6.0 I/O PORTS There are as many as thirty-five general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. 6.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins.
PIC16(L)F722A/723A 6.2 PORTA and the TRISA Registers PORTA is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 6-3). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). Example 6-1 shows how to initialize PORTA.
PIC16(L)F722A/723A 6.2.1 ANSELA REGISTER The ANSELA register (Register 6-4) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELA bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSELA bits has no affect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog.
PIC16(L)F722A/723A 6.2.2 PIN DESCRIPTIONS AND DIAGRAMS Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the A/D Converter (ADC), refer to the appropriate section in this data sheet. 6.2.2.1 RA0/AN0/SS/VCAP 6.2.2.6 Figure 6-4 shows the diagram for this pin. This pin is configurable to function as one of the following: • • • • • Figure 6-1 shows the diagram for this pin.
PIC16(L)F722A/723A FIGURE 6-1: BLOCK DIAGRAM OF RA0 PIC16F722A/723A only To Voltage Regulator VCAPEN = 00 VDD Data Bus D WR PORTA Q I/O Pin CK Q D WR TRISA VSS Q CK Q RD TRISA ANSA0 RD PORTA TO SSP SS Input To A/D Converter 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A FIGURE 6-2: RA<3:1> BLOCK DIAGRAM VDD Data Bus D WR PORTA Q I/O Pin CK Q D WR TRISA VSS Q CK Q RD TRISA ANSAx RD PORTA To A/D Converter FIGURE 6-3: BLOCK DIAGRAM OF RA4 VDD Data Bus D WR PORTA I/O Pin CK Q D WR TRISA Q Q VSS CK Q RD TRISA ANSA4 RD PORTA To Timer0 Clock MUX To Cap Sensor DS41417B-page 52 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A FIGURE 6-4: BLOCK DIAGRAM OF RA5 PIC16F722A/723A only To Voltage Regulator VCAPEN = 01 VDD Data Bus D WR PORTA Q I/O Pin CK Q D WR TRISA VSS Q CK Q RD TRISA ANSA5 RD PORTA To SSP SS Input To A/D Converter To Cap Sensor 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A FIGURE 6-5: BLOCK DIAGRAM OF RA6 PIC16F722A/723A only To Voltage Regulator VCAPEN = 10 Oscillator Circuit RA7/OSC1 CLKOUT(1) Enable Data Bus VDD I/O Pin FOSC/4 1 D WR PORTA Q 0 CK Q VSS D WR TRISA Q CK Q RD TRISA FOSC = LP or XT or HS (00X OR 010) RD PORTA Note 1: CLKOUT Enable = 1 when FOSC = RC or INTOSC (No I/O Selected).
PIC16(L)F722A/723A TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/ DONE ADON 92 ADCON1 — ADCS2 ADCS1 ADCS0 — — ADREF1 ADREF0 93 ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 49 — — — — — — SSSEL CCP2SEL 47 CPSON — — — T0XCS 121 Name APFCON CPSCON0 CPSCON1 OPTION_REG PORTA CPSRNG1 CPSRNG0 CPSOUT — — — — CPSCH3 CPSCH2 CPSCH1 CPSCH0 122 RB
PIC16(L)F722A/723A 6.3 PORTB and TRISB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 6-6). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16(L)F722A/723A REGISTER 6-5: PORTB: PORTB REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown RB<7:0>: PORTB I/O Pin bits 1 = Port pin is > VIH 0 = Port pin is < VIL REGISTER 6-6: TRISB: PORTB TRI-STATE REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
PIC16(L)F722A/723A REGISTER 6-8: IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown IOCB<7:0>: Interrupt-on-Change PORTB Control bits 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled REGISTER 6-9: ANSELB: POR
PIC16(L)F722A/723A 6.3.4 PIN DESCRIPTIONS AND DIAGRAMS Each PORTB pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the SSP, I2C or interrupts, refer to the appropriate section in this data sheet. 6.3.4.1 RB0/AN12/CPS0/INT Figure 6-7 shows the diagram for this pin.
PIC16(L)F722A/723A FIGURE 6-7: BLOCK DIAGRAM OF RB0 Data Bus D WR WPUB Q VDD CK Q Weak D WR PORTB Q I/O Pin CK Q D WR TRISB VDD RBPU RD WPUB VSS Q CK Q RD TRISB ANSB0 RD PORTB WR IOCB D Q Q CK Q D EN RD IOCB Q Q3 D EN Interrupt-onChange RD PORTB To External Interrupt Logic To A/D Converter To Cap Sensor DS41417B-page 60 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A FIGURE 6-8: BLOCK DIAGRAM OF RB4, RB<2:1> Data Bus D WR WPUB Q CK Q D VDD Q I/O Pin CK Q D WR TRISB Weak RBPU RD WPUB WR PORTB VDD VSS Q CK Q RD TRISB ANSB<4,2,1> RD PORTB WR IOCB D Q CK Q Q D EN RD IOCB Q D Q3 To A/D Converter To Cap Sensor EN Interrupt-onChange RD PORTB 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A FIGURE 6-9: BLOCK DIAGRAM OF RB3 Data Bus D WR WPUB Q VDD CCP2OUT 1 D Q 0 I/O Pin CK Q D WR TRISB Weak CCP2OUT Enable RBPU RD WPUB WR PORTB VDD CK Q VSS Q CK Q RD TRISB ANSB<5,3> RD PORTB WR IOCB D Q CK Q Q D EN RD IOCB Q Q3 D EN Interrupt-onChange RD PORTB To CCP2(1) To A/D Converter To Cap Sensor Note 1: CCP2 input is controlled by CCP2SEL in the APFCON register. DS41417B-page 62 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A FIGURE 6-10: BLOCK DIAGRAM OF RB5 Data Bus D WR WPUB Q VDD CCP2OUT 1 D Q 0 I/O Pin CK Q D WR TRISB Weak CCP2OUT Enable RBPU RD WPUB WR PORTB VDD CK Q VSS Q CK Q RD TRISB ANSB<5,3> RD PORTB WR IOCB D Q CK Q Q D EN RD IOCB Q Q3 D EN Interrupt-onChange RD PORTB To Timer1 Gate To A/D Converter To Cap Sensor 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A FIGURE 6-11: BLOCK DIAGRAM OF RB6 ICSP™ Mode Debug Data Bus D WR WPUB Q D WR IOCB 0 CK Q I/O Pin VSS Q 0 CK Q RD TRISB RD PORTB VDD 1 Q D WR TRISB Weak RBPU PORT_ICDCLK RD WPUB WR PORTB VDD CK Q 1 TRIS_ICDCLK D Q CK Q Q D EN RD IOCB Q Q3 D EN Interrupt-onChange RD PORTB ICSPCLK DS41417B-page 64 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A FIGURE 6-12: BLOCK DIAGRAM OF RB7 ICSP™ Mode Debug Data Bus D WR WPUB Q D WR IOCB 0 CK Q I/O Pin VSS Q 0 CK Q RD TRISB RD PORTB VDD 1 Q D WR TRISB Weak RBPU PORT_ICDDAT RD WPUB WR PORTB VDD CK Q 1 TRIS_ICDDAT D Q CK Q Q D EN RD IOCB Q Q3 D EN Interrupt-onChange RD PORTB ICSPDAT_IN 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A TABLE 6-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/ DONE ADON 92 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 58 APFCON — — — — — — SSSEL CCP2SEL 47 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 124 CPSCON0 CPSON — — — T0XCS 121 Name CPSCON1 CPSRNG1 CPSRNG0 CPSOUT — — — — CPSCH3 CPSCH2 CPSCH1 CPSCH0 122 GIE PEIE
PIC16(L)F722A/723A 6.4 PORTC and TRISC Registers PORTC is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISC (Register 6-11). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16(L)F722A/723A 6.4.1 RC0/T1OSO/T1CKI 6.4.8 RC7/RX/DT Figure 6-13 shows the diagram for this pin. This pin is configurable to function as one of the following: Figure 6-20 shows the diagram for this pin. This pin is configurable to function as one of the following: • General purpose I/O • Timer1 oscillator output • Timer1 clock input • General purpose I/O • Asynchronous serial input • Synchronous serial data I/O 6.4.2 RC1/T1OSI/CCP2 Figure 6-14 shows the diagram for this pin.
PIC16(L)F722A/723A FIGURE 6-13: BLOCK DIAGRAM OF RC0 Oscillator Circuit RC1/T1OSI Data Bus D WR PORTC VDD Q I/O Pin CK Q D WR TRISC VSS Q CK Q RD TRISC T1OSCEN RD PORTC To Timer1 CLK Input FIGURE 6-14: BLOCK DIAGRAM OF RC1 CCP2OUT Enable Data Bus CCP2OUT 1 D WR PORTC VDD 0 I/O Pin CK Q D WR TRISC Q Oscillator Circuit RC0/T1OSO Q VSS CK Q RD TRISC T1OSCEN RD PORTC To CCP2(1) Input Note 1: CCP2 input is controlled by CCP2SEL in the APFCON register.
PIC16(L)F722A/723A FIGURE 6-15: BLOCK DIAGRAM OF RC2 CCP1OUT Enable Data Bus VDD CCP1OUT 1 D WR PORTC Q 0 I/O Pin CK Q D WR TRISC VSS Q CK Q RD TRISC RD PORTC To CCP1 Input FIGURE 6-16: BLOCK DIAGRAM OF RC3 SSPM = SPI Mode SCK_MASTER Data Bus 0 D WR PORTC 1 1 0 Q VDD SSPEN (2) I/O Pin CK Q SCL D WR TRISC VSS Q CK Q RD TRISC To SSP SPI CLOCK Input 01 RD PORTC 10 SSPEN SSPM = I2C™ Mode TO SSP I2C™ SCL Input I2C™(1) Note 1: I2C™ Schmitt Trigger has special input levels.
PIC16(L)F722A/723A FIGURE 6-17: BLOCK DIAGRAM OF RC4 SSPEN SSPM = I2C™ Mode VDD Data Bus 1 D WR PORTC 0 Q (2) I/O Pin CK Q VSS D WR TRISC Q CK Q RD TRISC To SSP SPI Data Input 01 RD PORTC 10 SDA from SSP To SSP I2C™ SDA Input I2C™(1) Note 1: I2C™ Schmitt Trigger has special input levels. 2: I2C™ Slew Rate limiting controlled by SMP bit of SSPSTAT register.
PIC16(L)F722A/723A FIGURE 6-19: BLOCK DIAGRAM OF RC6 SYNC USART_TX 0 USART_CK 1 Data Bus D WR PORTC Q VDD 1 0 I/O Pin CK Q D WR TRISC VSS Q CK Q RD TRISC RD PORTC SPEN TXEN 0 CSRC 1 SYNC To USART Sync Clock Input FIGURE 6-20: BLOCK DIAGRAM OF RC7 SPEN SYNC VDD Data Bus USART_DT 1 D WR PORTC Q I/O Pin CK Q D WR TRISC 0 Q VSS CK Q RD TRISC RD PORTC SPEN SYNC TXEN SREN CREN To USART Data Input DS41417B-page 72 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A TABLE 6-4: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 APFCON — — — — — CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 RC7 RC6 RC5 RC4 RC3 CCP2CON PORTC Bit 5 Bit 4 Bit 3 Register on Page Bit 2 Bit 1 Bit 0 — SSSEL CCP2SEL 47 CCP1M0 124 CCP2M0 124 RC0 67 RC2 RC1 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 143 SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 162 SSPSTAT
PIC16(L)F722A/723A 6.5 PORTE and TRISE Registers PORTE(1) is an 1-bit wide, input only port. RE3 is input only and its TRIS bit will always read as ‘1’. Reading the PORTE register (Register 6-12) reads the status of the pins. RE3 reads ‘0’ when MCLRE = 1.
PIC16(L)F722A/723A 6.5.1 RE3/MCLR/VPP Figure 6-21 shows the diagram for this pin.
PIC16(L)F722A/723A NOTES: DS41417B-page 76 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A 7.0 OSCILLATOR MODULE 7.1 Overview Clock source modes are configured by the FOSC bits in Configuration Word 1 (CONFIG1). The oscillator module can be configured for one of eight modes of operation. The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 7-1 illustrates a block diagram of the oscillator module. 1. 2. 3.
PIC16(L)F722A/723A 7.2 Clock Source Modes Clock source modes can be classified as external or internal. • Internal clock source (INTOSC) is contained within the oscillator module and derived from a 500 kHz high precision oscillator. The oscillator module has eight selectable output frequencies, with a maximum internal frequency of 16 MHz. • External clock modes rely on external circuitry for the clock source.
PIC16(L)F722A/723A 7.4 Oscillator Control The Oscillator Control (OSCCON) register (Figure 7-1) displays the status and allows frequency selection of the internal oscillator (INTOSC) system clock.
PIC16(L)F722A/723A 7.5 Oscillator Tuning The INTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 7-2). When the OSCTUNE register is modified, the INTOSC frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. The default value of the OSCTUNE register is ‘0’. The value is a 6-bit two’s complement number.
PIC16(L)F722A/723A 7.6 External Clock Modes 7.6.1 OSCILLATOR START-UP TIMER (OST) If the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations on the OSC1 pin before the device is released from Reset. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended.
PIC16(L)F722A/723A FIGURE 7-4: CERAMIC RESONATOR OPERATION (XT OR HS MODE) FIGURE 7-5: EXTERNAL RC MODES VDD PIC® MCU REXT PIC® MCU OSC1/CLKIN Internal Clock OSC1/CLKIN CEXT C1 To Internal Logic RP(3) C2 Ceramic RS(1) Resonator RF(2) VSS Sleep OSC2/CLKOUT Recommended values: 10 k REXT 100 k, <3V 3 k REXT 100 k, 3-5V CEXT > 20 pF, 2-5V Note 1: A series resistor (RS) may be required for ceramic resonators with low drive level.
PIC16(L)F722A/723A 8.0 DEVICE CONFIGURATION 8.1 There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 register at 2007h and Configuration Word 2 register at 2008h. These registers are only accessible during programming. Device configuration consists of Configuration Word 1 and Configuration Word 2 registers, code protection and device ID.
PIC16(L)F722A/723A REGISTER 8-1: bit 2-0 CONFIG1: CONFIGURATION WORD REGISTER 1 (CONTINUED) FOSC<2:0>: Oscillator Selection bits 111 = RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN 110 = RCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN 101 = INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN 100 = INTOSCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN 011 = EC: I/O function on R
PIC16(L)F722A/723A 8.2 Code Protection If the code protection bit(s) have not been programmed, the on-chip program memory can be read out using ICSP™ for verification purposes. Note: 8.3 The entire Flash program memory will be erased when the code protection is turned off. See the “PIC16F72X/PIC16LF72X Memory Programming Specification” (DS41332) for more information.
PIC16(L)F722A/723A NOTES: DS41417B-page 86 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A 9.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 8-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter.
PIC16(L)F722A/723A 9.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Results formatting 9.1.1 For correct conversion, the appropriate TAD specification must be met. Refer to the A/D conversion requirements in Section 23.0 “Electrical Specifications” for more information.
PIC16(L)F722A/723A TABLE 9-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz Fosc/2 000 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s 100 200 ns (2) (2) (2) 1.0 s 4.0 s 400 ns (2) 1.0 s 2.0 s 8.0 s(3) Fosc/4 250 ns (2) 0.5 s 500 ns Fosc/8 001 Fosc/16 101 800 ns 1.0 s 2.0 s 4.0 s 16.0 s(3) Fosc/32 010 1.6 s 2.0 s 4.0 s 8.0 s(3) 32.
PIC16(L)F722A/723A 9.1.5 INTERRUPTS The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC interrupt flag is the ADIF bit in the PIR1 register. The ADC interrupt enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. 9.2.3 If a conversion must be terminated before completion, the GO/DONE bit can be cleared in software.
PIC16(L)F722A/723A 9.2.6 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8.
PIC16(L)F722A/723A 9.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC.
PIC16(L)F722A/723A REGISTER 9-2: ADCON1: A/D CONTROL REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 — ADCS2 ADCS1 ADCS0 — — ADREF1 ADREF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC (clock supplied from a dedicated RC oscillator) 100 = FOSC/
PIC16(L)F722A/723A 9.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 9-3. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 9-3.
PIC16(L)F722A/723A FIGURE 9-3: ANALOG INPUT MODEL VDD Rs VA VT 0.6V ANx CPIN 5 pF VT 0.6V RIC 1k Sampling Switch SS Rss I LEAKAGE(1) CHOLD = 10 pF VSS/VREF- Legend: CHOLD CPIN = Sample/Hold Capacitance = Input Capacitance 6V 5V VDD 4V 3V 2V I LEAKAGE = Leakage current at the pin due to various junctions = Interconnect Resistance RIC RSS = Resistance of Sampling Switch SS = Sampling Switch VT = Threshold Voltage RSS 5 6 7 8 9 10 11 Sampling Switch (k) Note 1: Refer to Section 23.
PIC16(L)F722A/723A TABLE 9-2: SUMMARY OF ASSOCIATED ADC REGISTERS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/ DONE ADON 92 ADCON1 — ADCS2 ADCS1 ADCS0 — — ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 49 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 58 Name ADRES A/D Result Register Byte — — DC2B1 DC2B0 FVRRDY FVREN — — CCP2CON FVRCON INTCON ADREF1 ADREF0 93 CCP2M3 CCP2M2 CCP2M1 CCP2M0 — 93
PIC16(L)F722A/723A 10.0 FIXED VOLTAGE REFERENCE This device contains an internal voltage regulator. To provide a reference for the regulator, a band gap reference is provided. This band gap is also user accessible via an A/D converter channel. User level band gap functions are controlled by the FVRCON register, which is shown in Register 10-1.
PIC16(L)F722A/723A NOTES: DS41417B-page 98 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A 11.0 TIMER0 MODULE When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. The Timer0 module is an 8-bit timer/counter with the following features: • • • • • • Note: 8-bit timer/counter register (TMR0) 8-bit prescaler (shared with Watchdog Timer) Programmable internal or external clock source Programmable external clock edge selection Interrupt on overflow TMR0 can be used to gate Timer1 11.1.
PIC16(L)F722A/723A 11.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The pres ca le values are selectable via the PS<2:0> bits of the OPTION register.
PIC16(L)F722A/723A REGISTER 11-1: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual PORT latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on r
PIC16(L)F722A/723A NOTES: DS41417B-page 102 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A 12.
PIC16(L)F722A/723A 12.1 Timer1 Operation 12.2 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. The TMR1CS<1:0> and T1OSCEN bits of the T1CON register are used to select the clock source for Timer1. Table 12-2 displays the clock source selections. 12.2.1 When used with an internal clock source, the module is a timer and increments on every instruction cycle.
PIC16(L)F722A/723A 12.3 Timer1 Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. 12.4 Timer1 Oscillator A dedicated low-power 32.768 kHz oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output).
PIC16(L)F722A/723A 12.6 Timer1 Gate 12.6.2.1 Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry. This is also referred to as Timer1 Gate Count Enable. Timer1 gate can also be driven by multiple selectable sources. 12.6.1 TIMER1 GATE COUNT ENABLE The Timer1 gate is enabled by setting the TMR1GE bit of the T1GCON register. The polarity of the Timer1 gate is configured using the T1GPOL bit of the T1GCON register.
PIC16(L)F722A/723A TABLE 12-5: WDT/TIMER1 GATE INTERACTION WDTE TMR1GE = 1 and T1GSS = 11 WDT Oscillator Enable WDT Reset Wake-up WDT Available for T1G Source 1 N Y Y Y N 1 Y Y Y Y Y 0 Y Y N N Y 0 N N N N N 12.6.3 TIMER1 GATE TOGGLE MODE When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate signal, as opposed to the duration of a single level pulse.
PIC16(L)F722A/723A 12.7 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • • • • TMR1ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. Note: 12.
PIC16(L)F722A/723A FIGURE 12-3: TIMER1 GATE COUNT ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL TIMER1 N FIGURE 12-4: N+1 N+2 N+3 N+4 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL TIMER1 N 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A FIGURE 12-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 TMR1GIF DS41417B-page 110 N Cleared by software N+1 N+2 Set by hardware on falling edge of T1GVAL Cleared by software 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A FIGURE 12-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 TMR1GIF N Cleared by software 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A 12.11 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register 12-1, is used to control Timer1 and select the various features of the Timer1 module.
PIC16(L)F722A/723A 12.12 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), shown in Register 12-2, is used to control Timer1 gate.
PIC16(L)F722A/723A TABLE 12-6: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 6 Bit 5 Bit 4 ANSELB — — ANSB5 ANSB4 ANSB3 CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 124 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 124 INTCON Bit 3 Bit 2 Bit 1 Bit 0 ANSB2 ANSB1 ANSB0 Register on Page Bit 7 58 GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 40 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 41 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CC
PIC16(L)F722A/723A 13.0 TIMER2 MODULE The Timer2 module is an 8-bit timer with the following features: • • • • • 8-bit timer register (TMR2) 8-bit period register (PR2) Interrupt on TMR2 match with PR2 Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘1’. Timer2 is turned off by clearing the TMR2ON bit to a ‘0’.
PIC16(L)F722A/723A REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 = 1:1 Postscaler 0001 = 1:2 Postscaler 0010 = 1:3 Postscaler 0011 = 1:4 Po
PIC16(L)F722A/723A 14.0 CAPACITIVE SENSING MODULE sensing module. The capacitive sensing module requires software and at least one timer resource to determine the change in frequency. Key features of this module include: The capacitive sensing module allows for an interaction with an end user without a mechanical interface. In a typical application, the capacitive sensing module is attached to a pad on a printed circuit board (PCB), which is electrically isolated from the end user.
PIC16(L)F722A/723A 14.1 Analog MUX 14.4.1 TIMER0 The capacitive sensing module can monitor up to 8 inputs. The capacitive sensing inputs are defined as CPS<7:0>.
PIC16(L)F722A/723A 14.5 Software Control The software portion of the capacitive sensing module is required to determine the change in frequency of the capacitive sensing oscillator. This is accomplished by the following: • Setting a fixed time base to acquire counts on Timer0 or Timer1 • Establishing the nominal frequency for the capacitive sensing oscillator • Establishing the reduced frequency for the capacitive sensing oscillator due to an additional capacitive load • Set the frequency threshold 14.5.
PIC16(L)F722A/723A 14.6 Operation During Sleep The capacitive sensing oscillator will continue to run as long as the module is enabled, independent of the part being in Sleep. In order for the software to determine if a frequency change has occurred, the part must be awake. However, the part does not have to be awake when the timer resource is acquiring counts. One way to acquire the Timer1 counts while in Sleep is to have Timer1 gated with the overflow of the Watchdog Timer.
PIC16(L)F722A/723A REGISTER 14-1: CPSCON0: CAPACITIVE SENSING CONTROL REGISTER 0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R-0 R/W-0 CPSON — — — CPSRNG1 CPSRNG0 CPSOUT T0XCS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CPSON: Capacitive Sensing Module Enable bit 1 = Capacitive sensing module is operating 0 = Capacitive sensing module is shut off and consumes no operati
PIC16(L)F722A/723A REGISTER 14-2: CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CPSCH2 CPSCH1 CPSCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 CPSCH<2:0>: Capacitive Sensing Channel Select bits If CPSON = 0: These bits are ignored. No channel is selected.
PIC16(L)F722A/723A 15.0 CAPTURE/COMPARE/PWM (CCP) MODULE The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate a Pulse-Width Modulated signal of varying frequency and duty cycle.
PIC16(L)F722A/723A REGISTER 15-1: CCPxCON: CCPx CONTROL REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DCxB<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the tw
PIC16(L)F722A/723A 15.1 Capture Mode 15.1.3 In Capture mode, CCPRxH:CCPRxL captures the 16-bit value of the TMR1 register when an event occurs on pin CCPx. An event is defined as one of the following and is configured by the CCPxM<3:0> bits of the CCPxCON register: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge 15.1.1 CCPx PIN CONFIGURATION In Capture mode, the CCPx pin should be configured as an input by setting the associated TRIS control bit.
PIC16(L)F722A/723A TABLE 15-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 58 APFCON — — — — — — SSSEL CCP2SEL 47 CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 124 — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 124 CCP2CON CCPRxL Capture/Compare/PWM Register X Low Byte CCPRxH Capture/Compare/PWM Register X High Byte Bit 0 Register on Page Bit 7 125 125 GIE PEIE T0
PIC16(L)F722A/723A 15.2 Compare Mode 15.2.2 In Compare mode, the 16-bit CCPRx register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCPx module may: • • • • • Toggle the CCPx output Set the CCPx output Clear the CCPx output Generate a Special Event Trigger Generate a Software Interrupt In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode.
PIC16(L)F722A/723A TABLE 15-4: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/ DONE ADON 92 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 58 APFCON — — — — — — SSSEL CCP2SEL 47 CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 124 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 124 Name CCPRxL Capture/Compare/PWM Register X Low Byte 125 CCPRxH C
PIC16(L)F722A/723A 15.3 PWM Mode The PWM mode generates a Pulse-Width Modulated signal on the CCPx pin. The duty cycle, period and resolution are determined by the following registers: • • • • The PWM output (Figure 15-4) has a time base (period) and a time that the output stays high (duty cycle). FIGURE 15-4: PR2 T2CON CCPRxL CCPxCON CCP PWM OUTPUT Period Pulse Width In Pulse-Width Modulation (PWM) mode, the CCP module produces up to a 10-bit resolution PWM output on the CCPx pin.
PIC16(L)F722A/723A 15.3.2 PWM PERIOD EQUATION 15-2: PULSE WIDTH The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 15-1. Pulse Width = CCPRxL:CCPxCON<5:4> EQUATION 15-1: Note: TOSC = 1/FOSC PWM PERIOD PWM Period = PR2 + 1 4 T OSC (TMR2 Prescale Value) Note: TOSC = 1/FOSC When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The CCPx pin is set.
PIC16(L)F722A/723A 15.3.4 PWM RESOLUTION EQUATION 15-4: The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. log 4 PR2 + 1 Resolution = ------------------------------------------ bits log 2 The maximum PWM resolution is 10 bits when PR2 is 255.
PIC16(L)F722A/723A TABLE 15-7: Name SUMMARY OF REGISTERS ASSOCIATED WITH PWM Bit 0 Register on Page ANSB1 ANSB0 58 SSSEL CCP2SEL 47 CCP1M2 CCP1M1 CCP1M0 124 CCP2M2 CCP2M1 CCP2M0 124 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 APFCON — — — — — — CCP1CON — — DC1B1 DC1B0 CCP1M3 — — DC2B1 DC2B0 CCP2M3 CCP2CON CCPRxL Capture/Compare/PWM Register X Low Byte 125 CCPRxH Capture/Compare/PWM Register X High Byte 125 PR2 Timer2 Peri
PIC16(L)F722A/723A 16.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (AUSART) The AUSART module includes the following capabilities: • • • • • • • • • • The Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution.
PIC16(L)F722A/723A FIGURE 16-2: AUSART RECEIVE BLOCK DIAGRAM SPEN CREN RX/DT Baud Rate Generator +1 SPBRG RSR Register MSb Pin Buffer and Control Data Recovery FOSC Multiplier x4 x16 x64 SYNC 1 0 0 BRGH x 1 0 Stop OERR (8) ••• 7 1 LSb 0 START RX9 ÷n n FERR RX9D RCREG Register 8 FIFO Data Bus RCIF RCIE Interrupt The operation of the AUSART module is controlled through two registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) These registers
PIC16(L)F722A/723A 16.1 AUSART Asynchronous Mode The AUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a ‘1’ data bit, and a VOL space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission.
PIC16(L)F722A/723A 16.1.1.4 TSR Status 16.1.1.6 The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: 16.1.1.5 1. 2. 3.
PIC16(L)F722A/723A FIGURE 16-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG Word 2 Word 1 BRG Output (Shift Clock) TX/CK pin Start bit TXIF bit (Transmit Buffer Empty Flag) INTCON bit 7/8 Stop bit Start bit bit 0 Word 2 Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg. This timing diagram shows two consecutive transmissions. TABLE 16-1: Name bit 1 Word 1 1 TCY TRMT bit (Transmit Shift Reg.
PIC16(L)F722A/723A 16.1.2 AUSART ASYNCHRONOUS RECEIVER The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 16-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate.
PIC16(L)F722A/723A 16.1.2.4 Receive Framing Error Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG.
PIC16(L)F722A/723A 16.1.2.8 1. 2. 3. 4. 5. 6. 7. 8. 9. Asynchronous Reception Set-up: 16.1.2.9 Initialize the SPBRG register and the BRGH bit to achieve the desired baud rate (refer to Section 16.2 “AUSART Baud Rate Generator (BRG)”). Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit reception is desired, set the RX9 bit.
PIC16(L)F722A/723A TABLE 16-2: Name REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 RCREG AUSART Receive Data Register INTCON 0000 0000 0000 0000 RCSTA SPEN RX
PIC16(L)F722A/723A REGISTER 16-1: R/W-0 CSRC TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 TX9 TXEN(1) SYNC — BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source)
PIC16(L)F722A/723A REGISTER 16-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit(1) 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit
PIC16(L)F722A/723A 16.2 AUSART Baud Rate Generator (BRG) EXAMPLE 16-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, and Asynchronous mode with SYNC = 0 and BRGH = 0 (as seen in Table 16-3): The Baud Rate Generator (BRG) is an 8-bit timer that is dedicated to the support of both the asynchronous and synchronous AUSART operation.
PIC16(L)F722A/723A TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0 BAUD RATE FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 16.0000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — — — — 1200 1221 1.73 255 1200 0.00 239 1201 0.08 207 1200 0.00 143 2400 2404 0.16 129 2400 0.
PIC16(L)F722A/723A TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 1200 — — — — — — — 1202 — 0.16 — 207 — 1200 — 0.00 — 191 300 1202 0.16 0.16 207 51 2400 2404 0.16 207 2404 0.16 103 2400 0.
PIC16(L)F722A/723A 16.3 AUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line.
PIC16(L)F722A/723A FIGURE 16-6: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 2 Word 1 TX/CK pin Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ Note: ‘1’ Synchronous Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
PIC16(L)F722A/723A 16.3.1.4 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the AUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register).
PIC16(L)F722A/723A FIGURE 16-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RCREG Note: Timing diagram demonstrates Synchronous Master mode with bit SREN = 1 and bit BRGH = 0.
PIC16(L)F722A/723A 16.3.2 SYNCHRONOUS SLAVE MODE If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: The following bits are used to configure the AUSART for Synchronous slave operation: • • • • • 1. SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 2. 3. 4. Setting the SYNC bit of the TXSTA register configures the device for synchronous operation.
PIC16(L)F722A/723A 16.3.2.3 AUSART Synchronous Slave Reception 16.3.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 16.3.1.4 “Synchronous Master Reception”), with the following exceptions: 1. 2. • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don’t care” in Slave mode 3. 4. A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep.
PIC16(L)F722A/723A 16.4 AUSART Operation During Sleep The AUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore can not generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers. 16.4.
PIC16(L)F722A/723A NOTES: DS41417B-page 154 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A 17.0 SSP MODULE OVERVIEW The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripherals or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C™) 17.1 A typical SPI connection between microcontroller devices is shown in Figure 17-1.
PIC16(L)F722A/723A FIGURE 17-2: SPI MODE BLOCK DIAGRAM Internal Data Bus Read Write SSPBUF Reg SSPSR Reg SDI bit 0 Shift Clock bit 7 SDO SS Control Enable RA5/SS RA0/SS SSSEL 2 Clock Select Edge Select 2 Edge Select Prescaler 4, 16, 64 SCK TRISx TMR2 Output FOSC 4 SSPM<3:0> DS41417B-page 156 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A 17.1.1 MASTER MODE In Master mode, data transfer can be initiated at any time because the master controls the SCK line. Master mode determines when the slave (Figure 17-1, Processor 2) transmits data via control of the SCK line. 17.1.1.1 Master Mode Operation The SSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF). The SSPSR register shifts the data in and out of the device, MSb first.
PIC16(L)F722A/723A FIGURE 17-3: SPI MASTER MODE WAVEFORM Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDO (CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 0 bit 7 Input Sample (SMP = 0) SDI (SMP = 1) bit 0 bit 7 Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF EXAMPLE 17-1: LOOP BANKSEL BTFSS GOTO BANKSEL MOVF MOVWF MOVF M
PIC16(L)F722A/723A 17.1.2 SLAVE MODE For any SPI device acting as a slave, the data is transmitted and received as external clock pulses appear on SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. 17.1.2.1 Slave Mode Operation The SSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first.
PIC16(L)F722A/723A FIGURE 17-4: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) bit 6 bit 7 bit 7 bit 5 bit 4 bit 3 bit 2 bit 1 b
PIC16(L)F722A/723A 17.1.2.4 Slave Select Operation The SS pin allows Synchronous Slave mode operation. The SPI must be in Slave mode with SS pin control enabled (SSPM<3:0> = 0100). The associated TRIS bit for the SS pin must be set, making SS an input. Note: In Slave Select mode, when: • SS = 0, The device operates as specified in Section 17.1.2 “Slave Mode”. • SS = 1, The SPI module is held in Reset and the SDO pin will be tri-stated.
PIC16(L)F722A/723A REGISTER 17-1: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared
PIC16(L)F722A/723A REGISTER 17-2: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (SPI MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SMP: SPI Data Input Sample Phase bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be
PIC16(L)F722A/723A TABLE 17-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION Bit 0 Register on Page ANSA1 ANSA0 49 SSSEL CCP2SEL 47 T0IF INTF RBIF 40 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 APFCON — — — — — — INTCON GIE PEIE T0IE INTE RBIE PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 41 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 43 PR2 Timer2 Period Register SSPBUF Synchronous
PIC16(L)F722A/723A I2C Mode 17.2 FIGURE 17-8: The SSP module, in I2C mode, implements all slave functions, except general call support. It provides interrupts on Start and Stop bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the I2C Standard mode specifications: VDD Data is sampled on the rising edge and shifted out on the falling edge of the clock. This ensures that the SDA signal is valid during the SCL high time.
PIC16(L)F722A/723A 17.2.2 START AND STOP CONDITIONS During times of no data transfer (Idle time), both the clock line (SCL) and the data line (SDA) are pulled high through external pull-up resistors. The Start and Stop conditions determine the start and stop of data transmission. The Start condition is defined as a high-to-low transition of the SDA line while SCL is high. The Stop condition is defined as a low-to-high transition of the SDA line while SCL is high.
PIC16(L)F722A/723A 17.2.4 ADDRESSING Once the SSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8 bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock line (SCL). 17.2.4.1 7-bit Addressing In 7-bit Addressing mode (Figure 17-10), the value of register SSPSR<7:1> is compared to the value of register SSPADD<7:1>. The address is compared on the falling edge of the eighth clock (SCL) pulse.
PIC16(L)F722A/723A 17.2.5 RECEPTION When the R/W bit of the received address byte is clear, the master will write data to the slave. If an address match occurs, the received address is loaded into the SSPBUF register. An address byte overflow will occur if that loaded address is not read from the SSPBUF before the next complete byte is received. An SSP interrupt is generated for each data transfer byte.
2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A 17.2.6 TRANSMISSION When the R/W bit of the received address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set and the slave will respond to the master by reading out data. After the address match, an ACK pulse is generated by the slave hardware and the SCL pin is held low (clock is automatically stretched) until the slave is ready to respond. See Section 17.2.7 “Clock Stretching”.
2010-2012 Microchip Technology Inc. CKP UA BF SSPIF 1 SCL S 1 2 1 4 1 5 0 6 7 A9 A8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 3 1 8 9 ACK R/W = 0 1 3 4 5 Cleared in software 2 7 UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address.
PIC16(L)F722A/723A 17.2.7 CLOCK STRETCHING 2 During any SCL low phase, any device on the I C bus may hold the SCL line low and delay, or pause, the transmission of data. This “stretching” of a transmission allows devices to slow down communication on the bus. The SCL line must be constantly sampled by the master to ensure that all devices on the bus have released SCL for more data. Stretching usually occurs after an ACK bit of a transmission, delaying the first bit of the next byte.
PIC16(L)F722A/723A 17.2.10 CLOCK SYNCHRONIZATION When the CKP bit is cleared, the SCL output is held low once it is sampled low. Therefore, the CKP bit will not stretch the SCL line until an external I2C master device has already asserted the SCL line low. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have released SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (Figure 17-14). FIGURE 17-14: 17.2.
PIC16(L)F722A/723A REGISTER 17-3: SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be c
PIC16(L)F722A/723A REGISTER 17-4: SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (I2C MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: SPI Data Input Sample Phase bit 1 = Slew Rate Control (limiting) disabled. Operating in I2C Standard mode (100 kHz and 1 MHz).
PIC16(L)F722A/723A REGISTER 17-5: SSPMSK: SSP MASK REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPADD to detect I2C address match 0 = The received address bit n is not used to detect I2C add
PIC16(L)F722A/723A 18.0 PROGRAM MEMORY READ The Flash program memory is readable during normal operation over the full VDD range of the device. To read data from program memory, five Special Function Registers (SFRs) are used: • • • • • PMCON1 PMDATL PMDATH PMADRL PMADRH The value written to the PMADRH:PMADRL register pair determines which program memory location is read. The read operation will be initiated by setting the RD bit of the PMCON1 register.
PIC16(L)F722A/723A REGISTER 18-1: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER R-1 U-0 U-0 U-0 U-0 U-0 U-0 R/S-0 Reserved — —l — — — — RD bit 7 bit 0 Legend: S = Setable bit, cleared in hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Reserved: Read as ‘1’. Maintain this bit set.
PIC16(L)F722A/723A REGISTER 18-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — PMA12 PMA11 PMA10 PMA9 PMA8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 PMA<12:8>: Program Memory Read Address bits REGISTER 18-5: x = Bit is unknown PMADRL: PROGRAM MEMORY ADDRESS LOW REGISTER R/W-x R/W-x
PIC16(L)F722A/723A NOTES: DS41417B-page 180 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A 19.0 POWER-DOWN MODE (SLEEP) The Power-down mode is entered by executing a SLEEP instruction. The following peripheral interrupts can wake the device from Sleep: 1. If the Watchdog Timer is enabled: 2. • • • • • • 3. 4. 5. 6. 7. WDT will be cleared but keeps running. PD bit of the STATUS register is cleared. TO bit of the STATUS register is set. Oscillator driver is turned off.
PIC16(L)F722A/723A 19.2 Wake-up Using Interrupts Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP.
PIC16(L)F722A/723A 20.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) The device is placed into Program/Verify mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP from 0v to VPP. In Program/Verify mode the Program Memory, User IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ISCPCLK pin is the clock input.
PIC16(L)F722A/723A NOTES: DS41417B-page 184 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A 21.0 INSTRUCTION SET SUMMARY The PIC16(L)F722A/723A instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction.
PIC16(L)F722A/723A TABLE 21-2: PIC16(L)F722A/723A INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f – f, d f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W
PIC16(L)F722A/723A 21.2 Instruction Descriptions ADDLW Add literal and W Syntax: [ label ] ADDLW Operands: 0 k 255 Operation: (W) + k (W) Status Affected: C, DC, Z Description: The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register. k BCF Bit Clear f Syntax: [ label ] BCF Operands: 0 f 127 0b7 Operation: 0 (f) Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared.
PIC16(L)F722A/723A BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT Operands: 0 f 127 0b<7 Operands: None Operation: 00h WDT 0 WDT prescaler, 1 TO 1 PD Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
PIC16(L)F722A/723A DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
PIC16(L)F722A/723A MOVWF Move W to f Syntax: [ label ] MOVF Move f Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 Operation: (W) (f) Operation: (f) (dest) Status Affected: None Status Affected: Z Description: Description: The contents of register f is moved to a destination dependent upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself.
PIC16(L)F722A/723A RETFIE Return from Interrupt RETLW Return with literal in W Syntax: [ label ] Syntax: [ label ] Operands: None Operands: 0 k 255 Operation: TOS PC, 1 GIE Operation: k (W); TOS PC Status Affected: None Status Affected: None Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
PIC16(L)F722A/723A RLF Rotate Left f through Carry SLEEP Enter Sleep mode Syntax: [ label ] Syntax: [ label ] SLEEP Operands: 0 f 127 d [0,1] Operands: None Operation: Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC16(L)F722A/723A SUBWF Subtract W from f XORLW Exclusive OR literal with W Syntax: [ label ] SUBWF f,d Syntax: [ label ] XORLW k Operands: 0 f 127 d [0,1] Operands: 0 k 255 (f) - (W) destination) Operation: Operation: (W) .XOR. k W) Status Affected: C, DC, Z Description: SWAPF Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register.
PIC16(L)F722A/723A NOTES: DS41417B-page 194 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A 22.
PIC16(L)F722A/723A 22.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 22.
PIC16(L)F722A/723A 22.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC16(L)F722A/723A 22.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 22.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC16(L)F722A/723A 23.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias....................................................................................................... -40°C to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS, PIC16F722A/723A ................................................................... -0.
PIC16(L)F722A/723A 23.1 DC Characteristics: PIC16(L)F722A/723A-I/E (Industrial, Extended) PIC16LF722A/723A Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F722A/723A Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param. No. D001 Sym. VDD Characteristic VDR Units PIC16LF722A/723A 1.8 1.8 2.3 2.
PIC16(L)F722A/723A FIGURE 23-1: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR VSS NPOR POR REARM VSS TVLOW(2) Note 1: 2: 3: TPOR(3) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical. 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A 23.2 DC Characteristics: PIC16(L)F722A/723A-I/E (Industrial, Extended) PIC16LF722A/723A Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F722A/723A Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Conditions Min. Typ† Max.
PIC16(L)F722A/723A 23.2 DC Characteristics: PIC16(L)F722A/723A-I/E (Industrial, Extended) (Continued) PIC16LF722A/723A Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F722A/723A Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Conditions Min. Typ† Max.
PIC16(L)F722A/723A 23.3 DC Characteristics: PIC16(L)F722A/723A-I/E (Power-Down) PIC16LF722A/723A Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F722A/723A Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Power-down Base Current Min. Typ† Max. +85°C Max.
PIC16(L)F722A/723A 23.3 DC Characteristics: PIC16(L)F722A/723A-I/E (Power-Down) (Continued) PIC16LF722A/723A Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F722A/723A Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Min.
PIC16(L)F722A/723A 23.4 DC Characteristics: PIC16(L)F722A/723A-I/E DC CHARACTERISTICS Param No. Sym. VIL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Min. Typ† Max. Units — — with Schmitt Trigger buffer with I2C™ levels Conditions — 0.8 V 4.5V VDD 5.5V — 0.15 VDD V 1.8V VDD 4.5V — — 0.2 VDD V 2.0V VDD 5.5V — — 0.
PIC16(L)F722A/723A 23.4 DC Characteristics: PIC16(L)F722A/723A-I/E (Continued) DC CHARACTERISTICS Param No. Sym. Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Min. Typ† Max. Units Conditions Cell Endurance 100 1k — E/W Temperature during programming: 10°C TA 40°C VDD for Read VMIN — — V Voltage on MCLR/VPP during Erase/Program 8.0 — 9.
PIC16(L)F722A/723A 23.5 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. TH01 TH02 TH03 TH04 TH05 Sym. Characteristic JA Thermal Resistance Junction to Ambient JC TJMAX PD Thermal Resistance Junction to Case Maximum Junction Temperature Power Dissipation PINTERNAL Internal Power Dissipation Typ. Units Conditions 60.0 C/W 28-pin SPDIP package 69.7 C/W 28-pin SOIC package 71.
PIC16(L)F722A/723A 23.6 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
PIC16(L)F722A/723A 23.7 AC Characteristics: PIC16F722A/723A-I/E FIGURE 23-3: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) PIC16F722A/723A VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C FIGURE 23-4: VDD (V) 5.5 3.6 2.5 2.3 2.0 1.8 0 4 10 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
PIC16(L)F722A/723A PIC16LF722A/723A VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C VDD (V) FIGURE 23-5: 3.6 2.5 2.3 2.0 1.8 0 4 16 10 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 23-1 for each Oscillator mode’s supported frequencies. FIGURE 23-6: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 + 5% 85 Temperature (°C) ± 3% 60 ± 2% 25 0 -20 -40 1.8 + 5% 2.0 2.5 3.0 3.3(2) 3.5 4.0 4.5 5.0 5.
PIC16(L)F722A/723A TABLE 23-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. OS01 Sym. FOSC Characteristic External CLKIN Frequency(1) Oscillator Frequency(1) OS02 TOSC External CLKIN Period(1) Oscillator Period(1) OS03 TCY Instruction Cycle Time(1) OS04* TosH, TosL External CLKIN High, External CLKIN Low TosR, TosF External CLKIN Rise, External CLKIN Fall OS05* Min. Typ† Max.
PIC16(L)F722A/723A TABLE 23-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. OS08 Sym. Characteristic HFOSC Internal Calibrated HFINTOSC Frequency(2) OS08A MFOSC Internal Calibrated MFINTOSC Frequency(2) OS10* Freq. Tolerance Min. Typ† Max. Units 2% — 16.0 — MHz 0°C TA +85°C, VDD 2.5V 5% — 16.0 — MHz -40°C TA +125°C 2% — 500 — kHz 0°C TA +85°C VDD 2.
PIC16(L)F722A/723A TABLE 23-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. OS11 OS12 Sym. TosH2ckL Characteristic Min. Typ† Max. Units Conditions — — 70 ns VDD = 3.3-5.0V — — 72 ns VDD = 3.3-5.
PIC16(L)F722A/723A FIGURE 23-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset (due to BOR) 33(1) Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. 2 ms delay if PWRTE = 0 and VREGEN = 1. 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A TABLE 23-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym. Characteristic Min. Typ† Max. Units Conditions 30 TMCL MCLR Pulse Width (low) 2 5 — — — — s s VDD = 3.3-5V, -40°C to +85°C VDD = 3.3-5V 31 TWDTLP Low Power Watchdog Timer Timeout Period (No Prescaler) 10 18 27 ms VDD = 3.
PIC16(L)F722A/723A TABLE 23-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym. TT0H 40* Characteristic T0CKI High Pulse Width Min. No Prescaler TT0L T0CKI Low Pulse Width No Prescaler Max. Units 0.5 TCY + 20 — — ns 10 — — ns With Prescaler 41* Typ† 0.
PIC16(L)F722A/723A TABLE 23-7: PIC16F722A/723A A/D CONVERTER (ADC) CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param Sym. No. Characteristic Min. Typ† Max. Units Conditions AD01 NR Resolution — — 8 AD02 EIL Integral Error — — ±1.7 AD03 EDL Differential Error — — ±1 AD04 EOFF Offset Error — — ±2.2 LSb VREF = 3.0V AD05 EGN LSb VREF = 3.
PIC16(L)F722A/723A FIGURE 23-12: PIC16F722A/723A A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO AD134 1 TCY (TOSC/2(1)) AD131 Q4 AD130 A/D CLK 7 A/D Data 6 5 4 3 2 1 0 NEW_DATA OLD_DATA ADRES 1 TCY ADIF GO Sample DONE Sampling Stopped AD132 Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
PIC16(L)F722A/723A FIGURE 23-14: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CK US121 US121 DT US122 US120 Note: Refer to Figure 23-2 for load conditions. TABLE 23-9: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. No. Symbol Characteristic Min. Max. Units US120 TCKH2DTV SYNC XMIT (Master and Slave) Clock high to data-out valid 3.0-5.5V — 80 ns 1.8-5.
PIC16(L)F722A/723A FIGURE 23-16: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SS SP70 SCK (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDO LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 23-2 for load conditions.
PIC16(L)F722A/723A FIGURE 23-18: SPI SLAVE MODE TIMING (CKE = 0) SS SP70 SCK (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 MSb SDO LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 23-2 for load conditions.
PIC16(L)F722A/723A TABLE 23-11: SPI MODE REQUIREMENTS Param No. Symbol Characteristic SP70* TSSL2SCH, SS to SCK or SCK input TSSL2SCL Min. Typ† Max.
PIC16(L)F722A/723A TABLE 23-12: I2C™ BUS START/STOP BITS REQUIREMENTS Param No. Symbol Characteristic SP90* TSU:STA SP91* THD:STA SP92* TSU:STO SP93 THD:STO Stop condition Start condition Typ 4700 — Max. Units — Setup time 400 kHz mode 600 — — Start condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — Stop condition 100 kHz mode 4700 — — Setup time Hold time * 100 kHz mode Min.
PIC16(L)F722A/723A TABLE 23-13: I2C™ BUS DATA REQUIREMENTS Param. No. Symbol SP100* THIGH Characteristic Clock high time Min. Max. Units Conditions 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1.5TCY — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.
PIC16(L)F722A/723A TABLE 23-14: CAP SENSE OSCILLATOR SPECIFICATIONS Param. No. CS01 CS02 CS03 Symbol ISRC ISNK VCHYST Characteristic Current Source Current Sink Cap Hysteresis Min. Typ† Max. Units High — -5.8 -6 A Medium — -1.1 -3.2 A Low — -0.2 -0.9 A High — 6.6 6 A Medium — 1.3 3.2 A Low — 0.24 0.
PIC16(L)F722A/723A 24.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
PIC16(L)F722A/723A FIGURE 24-2: PIC16LF722A/723A MAXIMUM IDD vs. FOSC OVER VDD, EC MODE 2,400 2,200 2,000 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 3.6V 3.3V 1,800 3V IDD (µA) 1,600 2.5V 1,400 1,200 2V 1,000 1.8V 800 600 400 200 0 1 MHz 4 MHz 8 MHz 12 MHz 16 MHz 20 MHz FOSC FIGURE 24-3: PIC16F722A/723A TYPICAL IDD vs. FOSC OVER VDD, EC MODE, VCAP = 0.
PIC16(L)F722A/723A FIGURE 24-4: PIC16LF722A/723A TYPICAL IDD vs. FOSC OVER VDD, EC MODE 2,200 2,000 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 3.6V 1,800 3.3V 3V 1,600 IDD (µA) 1,400 2.5V 1,200 2V 1,000 1.8V 800 600 400 200 0 1 MHz 4 MHz 8 MHz 12 MHz 16 MHz 20 MHz FOSC PIC16F722A/723A MAXIMUM IDD vs. VDD OVER FOSC, EXTRC MODE, VCAP = 0.
PIC16(L)F722A/723A FIGURE 24-6: PIC16LF722A/723A MAXIMUM IDD vs. VDD OVER FOSC, EXTRC MODE 500 450 4 MHz Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 400 350 IDD (µA) 300 250 200 150 1 MHz 100 50 0 1.8 2 2.5 3 3.3 3.6 VDD (V) PIC16F722A/723A TYPICAL IDD vs. VDD OVER FOSC, EXTRC MODE, VCAP = 0.
PIC16(L)F722A/723A FIGURE 24-8: PIC16LF722A/723A TYPICAL IDD vs. VDD OVER FOSC, EXTRC MODE 450 400 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 4 MHz 350 IDD (µA) 300 250 200 150 1 MHz 100 50 0 1.8 2 2.5 3 3.3 3.6 VDD (V) PIC16F722A/723A MAXIMUM IDD vs. FOSC OVER VDD, HS MODE, VCAP = 0.1µF FIGURE 24-9: 2.4 2.2 2 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 5V 4.5V 3.6V 1.8 3V 1.6 IDD (mA) 1.4 1.2 1 0.8 0.
PIC16(L)F722A/723A FIGURE 24-10: PIC16LF722A/723A MAXIMUM IDD vs. FOSC OVER VDD, HS MODE 2.50 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 3.6V 2.00 3.3V 3V 1.50 IDD (mA) 2.5V 1.00 0.50 0.00 4 MHz 6 MHz 8 MHz 10 MHz 13 MHz 16 MHz 20 MHz Fosc FIGURE 24-11: 2.00 PIC16F722A/723A TYPICAL IDD vs. FOSC OVER VDD, HS MODE, VCAP = 0.1µF Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 5V 4.5V 3.6V 3V IDD (mA) 1.
PIC16(L)F722A/723A FIGURE 24-12: PIC16LF722A/723A TYPICAL IDD vs. FOSC OVER VDD, HS MODE 2.50 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 2.00 3.6V 3.3V 3V IDD (mA) 1.50 2.5V 1.00 0.50 0.00 4 MHz 6 MHz 8 MHz 10 MHz 13 MHz 16 MHz 20 MHz Fosc FIGURE 24-13: PIC16F722A/723A MAXIMUM IDD vs. VDD OVER FOSC, XT MODE, VCAP = 0.
PIC16(L)F722A/723A FIGURE 24-14: PIC16LF722A/723A MAXIMUM IDD vs. VDD OVER FOSC, XT MODE 600 500 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 4 MHz IDD (µA) 400 300 1 MHz 200 100 0 1.8 2 2.5 3 3.3 3.6 VDD (V) FIGURE 24-15: PIC16F722A/723A TYPICAL IDD vs. VDD OVER FOSC, XT MODE, VCAP = 0.1µF 600 500 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 4 MHz IDD (µA) 400 300 1 MHz 200 100 0 1.8 2 2.5 3 3.
PIC16(L)F722A/723A FIGURE 24-16: PIC16LF722A/723A TYPICAL IDD vs. VDD OVER FOSC, XT MODE 600 500 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 4 MHz IDD (µA) 400 300 1 MHz 200 100 0 1.8 2 2.5 3 3.3 3.6 VDD (V) FIGURE 24-17: PIC16F722A/723A IDD vs. VDD, LP MODE, VCAP = 0.1µF 20.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 17.5 IDD (µA) 32 kHz Maximum 15.0 VDD (V) 32 kHz Typical 12.5 10.0 1.
PIC16(L)F722A/723A FIGURE 24-18: PIC16LF722A/723A IDD vs. VDD, LP MODE 30 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 25 32 kHz Maximum IDD (µA) 20 15 32 kHz Typical 10 5 1.8 3 3.3 3.6 VDD (V) FIGURE 24-19: PIC16F722A/723A MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE, VCAP = 0.1µF 210 200 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 5V 190 180 3.6V IDD (µA) 170 2.5V 160 150 1.8V 140 130 120 110 62.
PIC16(L)F722A/723A FIGURE 24-20: PIC16LF722A/723A MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE 170 160 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 3.6V IDD (µA) 150 3V 2.5V 140 130 1.8V 120 110 100 62.5 kHz 125 kHz 250 kHz 500 kHz FOSC FIGURE 24-21: PIC16F722A/723A MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE, VCAP = 0.1µF 2,000 1,800 5V Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 3.6V 1,600 2.
PIC16(L)F722A/723A FIGURE 24-22: PIC16LF722A/723A MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE 2,250 2,000 s Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 3.6V 1,750 3V 1,500 IDD (µA) 2.5V 1,250 1.8V 1,000 750 500 250 0 2 MHz 4 MHz 8 MHz 16 MHz FOSC FIGURE 24-23: PIC16F722A/723A TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE, VCAP = 0.
PIC16(L)F722A/723A FIGURE 24-24: PIC16LF722A/723A TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE 140 130 3.6V Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 3V 120 2.5V IDD (µA) 110 100 1.8V 90 80 70 62.5 kHz 125 kHz 250 kHz 500 kHz FOSC FIGURE 24-25: PIC16F722A/723A TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE, VCAP = 0.1µF 2,000 1,800 1,600 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 5V 3.6V 1,400 2.
PIC16(L)F722A/723A FIGURE 24-26: PIC16LF722A/723A TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE 2,000 3.6V Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 1,800 1,600 3V 1,400 2.5V IDD (µA) 1,200 1,000 1.8V 800 600 400 200 0 2 MHz 4 MHz 8 MHz 16 MHz VDD (V) FIGURE 24-27: PIC16F722A/723A MAXIMUM BASE IPD vs. VDD, VCAP = 0.1µF 25 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 20 125°C IPD (µA) 15 85°C 10 5 0 1.
PIC16(L)F722A/723A FIGURE 24-28: PIC16LF722A/723A MAXIMUM BASE IPD vs. VDD 7 6 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 125°C IPD (µA) 5 4 3 2 85°C 1 0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 24-29: PIC16F722A/723A TYPICAL BASE IPD vs. VDD, VCAP = 0.1µF 8 7 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 6 IPD (µA) 25°C 5 4 3 2 1.8V 2V 3V 3.6V 4V 5V 5.
PIC16(L)F722A/723A FIGURE 24-30: PIC16LF722A/723A TYPICAL BASE IPD vs. VDD 250 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 200 25°C IPD (nA) 150 100 50 0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 24-31: PIC16F722A/723A FIXED VOLTAGE REFERENCE IPD vs. VDD, VCAP = 0.1µF 70 60 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C 50 Max. 85°C IPD (µA) 40 30 Typ. 25°C 20 10 0 1.8V 2V 3V 3.6V 5V 5.
PIC16(L)F722A/723A FIGURE 24-32: PIC16LF722A/723A FIXED VOLTAGE REFERENCE IPD vs. VDD 25 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C 20 15 IPD (µA) Max. 85°C 10 Typ. 25°C 5 0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 24-33: PIC16F722A/723A BOR IPD vs. VDD, VCAP = 0.1µF 70 60 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C 50 IPD (µA) 40 Max. 85°C 30 Typ. 25°C 20 10 0 2V 3V 3.6V 5V 5.
PIC16(L)F722A/723A FIGURE 24-34: PIC16LF722A/723A BOR IPD vs. VDD 30 25 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C IPD (µA) 20 15 Max. 85°C 10 Typ. 25°C 5 0 2V 2.5V 3V 3.6V VDD (V) FIGURE 24-35: PIC16F722A/723A CAP SENSE HIGH POWER IPD vs. VDD, VCAP = 0.1µF 70 60 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C Max. 85°C 50 Typ. 25°C IPD (µA) 40 30 20 10 0 1.8V 2V 3V 3.
PIC16(L)F722A/723A FIGURE 24-36: PIC16LF722A/723A CAP SENSE HIGH POWER IPD vs. VDD 60 50 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C Max. 85°C 40 IPD (µA) Typ. 25°C 30 20 10 0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 24-37: PIC16F722A/723A CAP SENSE MEDIUM POWER IPD vs. VDD, VCAP = 0.1µF 30 25 Max. 125°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 20 IPD (µA) Max. 85°C 15 Typ. 25°C 10 5 0 1.
PIC16(L)F722A/723A FIGURE 24-38: PIC16LF722A/723A CAP SENSE MEDIUM POWER IPD vs. VDD 20 18 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C 16 14 IPD (µA) 12 10 8 Max. 85°C 6 Typ. 25°C 4 2 0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 24-39: PIC16F722A/723A CAP SENSE LOW POWER IPD vs. VDD, VCAP = 0.1µF 30 25 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C IPD (µA) 20 Max. 85°C 15 10 Typ.
PIC16(L)F722A/723A FIGURE 24-40: PIC16LF722A/723A CAP SENSE LOW POWER IPD vs. VDD 18 16 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C 14 12 IPD (µA) 10 8 6 Max. 85°C 4 Typ. 25°C 2 0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 24-41: PIC16F722A/723A T1OSC 32 kHz IPD vs. VDD, VCAP = 0.1µF 16 14 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 85°C 12 IPD (µA) 10 Typ. 25° C 8 6 4 2 0 1.
PIC16(L)F722A/723A FIGURE 24-42: PIC16LF722A/723A T1OSC 32 kHz IPD vs. VDD 4.0 3.5 Max. 85°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 3.0 2.5 IPD (µA) Typ. 2.0 1.5 1.0 0.5 0.0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 24-43: PIC16F722A/723A TYPICAL ADC IPD vs. VDD, VCAP = 0.1µF 7.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Typ. 25°C 7.0 IPD (µA) 6.5 6.0 5.5 5.0 1.8V 2V 3V 3.6V 5V 5.
PIC16(L)F722A/723A FIGURE 24-44: PIC16LF722A/723A TYPICAL ADC IPD vs. VDD 250 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Typ. 25°C 200 IPD (nA) 150 100 50 0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 24-45: PIC16F722A/723A ADC IPD vs. VDD, VCAP = 0.1µF 25 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C IPD (µA) 20 15 Max. 85°C 10 5 1.8V 2V 3V 3.6V 5V 5.
PIC16(L)F722A/723A FIGURE 24-46: PIC16LF722A/723A ADC IPD vs. VDD 8 7 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C 6 IPD (µA) 5 4 3 2 Max. 85°C 1 0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 24-47: PIC16F722A/723A WDT IPD vs. VDD, VCAP = 0.1µF 18 16 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 85°C 14 12 IPD (µA) 10 Typ. 25°C 8 6 4 2 0 1.8V 2V 3V 3.6V 5V 5.
PIC16(L)F722A/723A FIGURE 24-48: PIC16LF722A/723A WDT IPD vs. VDD 3.5 3.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 85°C 2.5 IPD (µA) 2.0 1.5 Typ. 25°C 1.0 0.5 0.0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 24-49: TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE 1.8 1.6 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 1.4 Max. -40° VIN (V) 1.2 Typ. 25° 1 Min. 125° 0.8 0.6 0.4 1.8 3.6 5.
PIC16(L)F722A/723A FIGURE 24-50: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE 3.5 3.0 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) VIHMax. -40°C 2.5 VIN (V) 2.0 1.5 VIHMin. 125°C 1.0 0.5 0.0 1.8 3.6 5.5 VDD (V) FIGURE 24-51: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE 3.0 2.5 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) VIL Max. -40°C VIN (V) 2.0 1.5 1.
PIC16(L)F722A/723A FIGURE 24-52: VOH vs. IOH OVER TEMPERATURE, VDD = 5.5V 5.6 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 5.5 VOH (V) 5.4 5.3 Max. -40° Typ. 25° 5.2 Min. 125° 5.1 5 -0.2 -1.0 -1.8 -2.6 -3.4 -4.2 -5.0 IOH (mA) FIGURE 24-53: VOH vs. IOH OVER TEMPERATURE, VDD = 3.6V 3.8 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 3.6 3.4 VOH (V) Max. -40° 3.2 Typ. 25° 3 Min. 125° 2.8 2.
PIC16(L)F722A/723A FIGURE 24-54: VOH vs. IOH OVER TEMPERATURE, VDD = 1.8V 2 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 1.8 1.6 Max. -40° 1.4 VOH (V) 1.2 Typ. 25° 1 0.8 0.6 Min. 125° 0.4 0.2 0 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 IOH (mA) FIGURE 24-55: VOL vs. IOL OVER TEMPERATURE, VDD = 5.5V 0.5 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 0.45 0.4 0.35 Max.
PIC16(L)F722A/723A FIGURE 24-56: VOL vs. IOL OVER TEMPERATURE, VDD = 3.6 0.9 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 0.8 0.7 0.6 Max. 125° VOL (V) 0.5 0.4 Typ. 25° 0.3 0.2 Min. -40° 0.1 0 4.0 5.0 FIGURE 24-57: 6.0 7.0 IOL (mA) 8.0 9.0 10.0 VOL vs. IOL OVER TEMPERATURE, VDD = 1.8V 1.2 1 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 0.8 VOL (V) Max. 125° 0.6 0.4 0.2 Min. -40° 0 0.0 0.
PIC16(L)F722A/723A FIGURE 24-58: PIC16F722A/723A PWRT PERIOD 105 95 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. -40°C TIME (ms) 85 75 Typ. 25°C 65 Min. 125°C 55 45 1.8V 2V 2.2V 2.4V 3V 3.6V 4V 4.5V 5V 5.5V VDD FIGURE 24-59: PIC16F722A/723A WDT TIME-OUT PERIOD 24.00 22.00 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. -40°C 20.00 TIME (ms) 18.00 Typ. 25°C 16.00 14.00 Min. 125°C 12.00 10.
PIC16(L)F722A/723A FIGURE 24-60: PIC16F722A/723A HFINTOSC WAKE-UP FROM SLEEP START-UP TIME 6.0 5.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 5.0 4.5 Max. TIME (us) 4.0 3.5 3.0 Typ. 2.5 2.0 1.5 1.0 1.8V 2V 3V 3.6V 4V 4.5V 5V 5.5V VDD FIGURE 24-61: PIC16F722A/723A A/D INTERNAL RC OSCILLATOR PERIOD 6.0 5.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Period (µs) 4.0 3.0 Max. Min. 2.0 1.0 0.0 1.
PIC16(L)F722A/723A FIGURE 24-62: PIC16F722A/723A CAP SENSE OUTPUT CURRENT, POWER MODE = HIGH 20000 Min. Sink -40°C 15000 Typ. Sink 25°C Current (nA) 10000 Max. Sink 85°C 5000 0 Min. Source 85°C -5000 Typ. Source 25°C -10000 Max. Source -40°C -15000 1.8 2 2.5 3 3.2 3.6 4 4.5 5 5.5 VDD(V) FIGURE 24-63: PIC16F722A/723A CAP SENSE OUTPUT CURRENT, POWER MODE = MEDIUM 3000 Max. Sink -40°C 2000 Typ. Sink 25°C 1000 Current (nA) Min. Sink 85°C 0 Min. Source 85°C -1000 Typ.
PIC16(L)F722A/723A FIGURE 24-64: PIC16F722A/723A CAP SENSE OUTPUT CURRENT, POWER MODE = LOW 600 Max. Sink 85°C 400 Typ. Sink 25°C 200 Min. Sink -40°C Current (nA) 0 Min. Source 85°C -200 Typ. Source 25°C -400 -600 Max. Source -40°C -800 1.8 2 2.5 3 3.2 3.6 4 4.5 5 5.5 VDD(V) FIGURE 24-65: PIC16F722A/723A CAP SENSOR HYSTERESIS, POWER MODE = HIGH 700 Max. 125°C Max. 85°C 600 mV Typ. 25°C 500 Min. 0°C Min. -40°C 400 300 1.8 2.0 2.5 3.0 3.2 3.6 4.0 4.5 5.0 5.
PIC16(L)F722A/723A FIGURE 24-66: PIC16F722A/723A CAP SENSOR HYSTERESIS, POWER MODE = MEDIUM 550 500 Max. 125°C mV 450 Max. 85°C 400 Typ. 25°C 350 Min. 0°C 300 Min. -40°C 250 1.8 2.0 2.5 3.0 3.2 3.6 4.0 4.5 5.0 5.5 VDD(V) FIGURE 24-67: PIC16F722A/723A CAP SENSOR HYSTERESIS, POWER MODE = LOW 450 Max. 125°C 400 Max. 85°C mV 350 300 Typ. 25°C 250 Min. 0°C 200 Min -40°C 150 1.8 2.0 2.5 3.0 3.2 3.6 4.0 4.5 5.0 5.
PIC16(L)F722A/723A FIGURE 24-68: TYPICAL FVR (X1 AND X2) VS. SUPPLY VOLTAGE (V) NORMALIZED AT 3.0V 1.5 Percent Change (%) 1 0.5 0 -0.5 -1 -1.5 1.8 2.5 3 3.6 4.2 5.5 Voltage FIGURE 24-69: TYPICAL FVR CHANGE VS. TEMPERATURE NORMALIZED AT 25°C 1.5 1 Percent Change (%) 0.5 0 -0.5 -1 -1.5 -2 -2.5 -3 -40 0 45 85 125 Temperature (°C) 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A NOTES: DS41417B-page 262 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A 25.0 PACKAGING INFORMATION 25.1 Package Marking Information 28-Lead SPDIP (.300”) Example PIC16F722A -I/SP e3 0810017 28-Lead QFN (6x6 mm) PIN 1 XXXXXXXX XXXXXXXX YYWWNNN Example PIN 1 16F722A -I/ML e3 0810017 28-Lead UQFN (4x4x0.5 mm) PIN 1 PIN 1 Legend: XX...
PIC16(L)F722A/723A 25.1 Package Marking Information (Continued) 28-Lead SOIC (7.50 mm) XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX Example PIC16F722A -I/SO e3 0810017 YYWWNNN 28-Lead SSOP (5.30 mm) Example PIC16F722A -I/SS e3 0810017 Legend: XX...
PIC16(L)F722A/723A 25.2 Package Details The following sections give the technical details of the packages.
PIC16(L)F722A/723A /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 0/ ± [ PP %RG\ >4)1@ ZLWK PP &RQWDFW /HQJWK 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D2 EXPOSED PAD e E b E2 2 2 1 1 N K N NOTE 1 L BOTTOM VIEW TOP VIEW A A3 A1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO +HLJKW $ 6WDQGRII $ &RQWDFW 7
PIC16(L)F722A/723A /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 0/ ± [ PP %RG\ >4)1@ ZLWK PP &RQWDFW /HQJWK 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41417B-page 268 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41417B-page 270 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41417B-page 272 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A /HDG 3ODVWLF 6KULQN 6PDOO 2XWOLQH 66 ± PP %RG\ >6623@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D N E E1 1 2 NOTE 1 b e c A2 A φ A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ± ± 2YHUDOO :LGWK ( 0RO
PIC16(L)F722A/723A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41417B-page 274 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A APPENDIX A: DATA SHEET REVISION HISTORY Revision A (April 2010) Original release of this data sheet. APPENDIX B: MIGRATING FROM OTHER PIC® DEVICES This discusses some of the issues in migrating from other PIC® devices to the PIC16F722A/723A family of devices. Revision B (January 2012) Updated the data sheet to new format; Updated Figure 9-1 and Register 9-1; Updated the Packaging Information section; Updated the Product Identification System section; Other minor corrections.
PIC16(L)F722A/723A NOTES: DS41417B-page 276 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A INDEX A Reception ......................................................... 152 Transmission .................................................... 151 A/D Specifications............................................................ 218 Absolute Maximum Ratings .............................................. 199 AC Characteristics Industrial and Extended ............................................ 210 Load Conditions ........................................................ 209 ADC .........
PIC16(L)F722A/723A CCPx Pin Configuration ............................................ 125 Compare Mode ......................................................... 127 CCPx Pin Configuration .................................... 127 Software Interrupt Mode ........................... 125, 127 Special Event Trigger........................................ 127 Timer1 Mode Selection ............................. 125, 127 Interaction of Two CCP Modules (table) ................... 123 Prescaler .....................
PIC16(L)F722A/723A SUBWF ..................................................................... 193 SWAPF ..................................................................... 193 XORLW..................................................................... 193 XORWF..................................................................... 193 Summary Table......................................................... 186 INTCON Register ................................................................
PIC16(L)F722A/723A RC7 ............................................................................. 68 Specifications ............................................................ 214 PORTC Register ................................................................. 67 PORTE................................................................................ 74 Associated Registers .................................................. 74 PORTE Register .........................................................
PIC16(L)F722A/723A T T1CON Register ......................................................... 19, 112 TMR1ON Bit.............................................................. 113 T1GCON Register............................................................. 113 T2CON Register ................................................. 19, 116, 164 Thermal Considerations .................................................... 208 Time-out Sequence............................................................. 32 Timer0 .....
PIC16(L)F722A/723A NOTES: DS41417B-page 282 2010-2012 Microchip Technology Inc.
PIC16(L)F722A/723A THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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PIC16(L)F722A/723A PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Device _ [X](1) PART NO.
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