Datasheet

PIC16F72X/PIC16LF72X
DS41341E-page 76 © 2009 Microchip Technology Inc.
FIGURE 6-15: BLOCK DIAGRAM OF RC2
FIGURE 6-16: BLOCK DIAGRAM OF RC3
0
1
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
RD
WR
WR
RD
Data Bus
PORTC
TRISC
TRISC
PORTC
To CCP1 Input
CCP1OUT
CCP1OUT
Enable
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
RD
WR
WR
RD
Data Bus
PORTC
TRISC
TRISC
PORTC
To SSP SPI
0
1
SSPEN
SSPM = I
2
C™ MODE
SCL
SSPEN
0
1
SCK_MASTER
SSPM = SPI MODE
To SSP I
2
C™
Clock Input
SCL Input
0
1
1
0
(2)
I
2
C™
(1)
Note 1: I
2
C™ Schmitt Trigger has special input levels.
2: I
2
C™ Slew Rate limiting controlled by SMP bit of SSPSTAT register.