Datasheet
PIC16F72X/PIC16LF72X
DS41341E-page 6 © 2009 Microchip Technology Inc.
TABLE 1: 28-PIN PDIP/SOIC/SSOP/QFN/UQFN SUMMARY
(PIC16F722/723/726/PIC16LF722/723/726)
I/O
28-Pin
PDIP,
SOIC,
SSOP
28-Pin
QFN,
UQFN
A/D Cap Sensor Timers CCP AUSART SSP Interrupt Pull-Up Basic
RA0 2 27 AN0 — — — — SS
(3)
— — VCAP
(4)
RA1 3 28 AN1 — — — — — — — —
RA2 4 1 AN2 — — — — — — — —
RA3 5 2
AN3/V
REF
———————
—
RA4 6 3 — CPS6 T0CKI — — — — — —
RA5 7 4 AN4 CPS7 — — — SS
(3)
—— VCAP
(4)
RA6 10 7 — — — — — — — — OSC2/CLKOUT/VCAP
(4)
RA7 9 6 — — — — — — — — OSC1/CLKIN
RB0 21 18 AN12 CPS0 — — — — IOC/INT Y —
RB1 22 19 AN10 CPS1 — — — — IOC Y —
RB2 23 20 AN8 CPS2 — — — — IOC Y —
RB3 24 21 AN9 CPS3 — CCP2
(2)
— — IOC Y —
RB4 25 22 AN11 CPS4 — — — — IOC Y —
RB5 26 23 AN13 CPS5 T1G — — — IOC Y —
RB6 27 24 — — — — — — IOC Y ICSPCLK/ICDCLK
RB7 28 25 — — — — — — IOC Y ICSPDAT/ICDDAT
RC0 11 8 — — T1OSO/T1CKI — — — — — —
RC1 12 9 — — T1OSI CCP2
(2)
———— —
RC2 13 10 — — — CCP1 — — — — —
RC3 14 11 — — — — — SCK/SCL — — —
RC4 15 12 — — — — SDI/SDA — — —
RC5 16 13 — — — — — SDO — — —
RC6 17 14 — — — — TX/CK — — — —
RC7 18 15 — — — — RX/DT — — — —
RE3 1 26 — — — — — — — Y
(1)
MCLR/VPP
—2017 — — — — — — — — VDD
— 8,19 5,16 — — — — — — — — VSS
Note 1: Pull-up enabled only with external MCLR configuration.
2: RC1 is the default pin location for CCP2. RB3 may be selected by changing the CCP2SEL bit in the APFCON register.
3: RA5 is the default pin location for SS
. RA0 may be selected by changing the SSSEL bit in the APFCON register.
4: PIC16F72X devices only.
Note: The PIC16F72X devices have an internal low dropout voltage regulator. An external capacitor must be
connected to one of the available V
CAP pins to stabilize the regulator. For more information, see
Section 5.0 “Low Dropout (LDO) Voltage Regulator”. The PIC16LF72X devices do not have the voltage
regulator and therefore no external capacitor is required.