Datasheet

PIC16F72X/PIC16LF72X
DS41341E-page 48 © 2009 Microchip Technology Inc.
4.5.3 PIE2 REGISTER
The PIE2 register contains the interrupt enable bits, as
shown in Register 4-3.
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 4-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — CCP2IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-1 Unimplemented: Read as ‘0’
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt