Datasheet

© 2009 Microchip Technology Inc. DS41341E-page 187
PIC16F72X/PIC16LF72X
REGISTER 17-4: SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (I
2
C MODE)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A
PSR/WUA BF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SMP: SPI Data Input Sample Phase bit
1 = Slew Rate Control (limiting) disabled. Operating in I
2
C Standard Mode (100 kHz and 1 MHz).
0 = Slew Rate Control (limiting) enabled. Operating in I
2
C Fast Mode (400 kHz).
bit 6 CKE: SPI Clock Edge Select bit
This bit must be maintained clear. Used in SPI mode only.
bit 5 D/A
: DATA/ADDRESS bit (I
2
C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit
This bit is cleared when the SSP module is disabled, or when the Start bit is detected last.
1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0 = Stop bit was not detected last
bit 3 S: Start bit
This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last.
1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0 = Start bit was not detected last
bit 2 R/W
: READ/WRITE bit Information
This bit holds the R/W
bit information following the last address match. This bit is only valid from the address match
to the next Start bit, Stop bit or ACK
bit.
1 = Read
0 = Write
bit 1 UA: Update Address bit (10-bit I
2
C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
Receive
:
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit
:
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty