Datasheet

 2010-2012 Microchip Technology Inc. DS41417B-page 89
PIC16(L)F722A/723A
TABLE 9-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
FIGURE 9-2: ANALOG-TO-DIGITAL CONVERSION T
AD CYCLES
ADC Clock Period (TAD) Device Frequency (FOSC)
ADC
Clock Source
ADCS<2:0> 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz
Fosc/2 000
100 ns
(2)
125 ns
(2)
250 ns
(2)
500 ns
(2)
2.0 s
Fosc/4 100 200 ns
(2)
250 ns
(2)
500 ns
(2)
1.0 s4.0 s
Fosc/8 001
400 ns
(2)
0.5 s
(2)
1.0 s2.0 s 8.0 s
(3)
Fosc/16 101 800 ns 1.0 s2.0 s4.0 s 16.0 s
(3)
Fosc/32 010 1.6 s2.0 s4.0 s 8.0 s
(3)
32.0 s
(3)
Fosc/64 110 3.2 s4.0 s 8.0 s
(3)
16.0 s
(3)
64.0 s
(3)
FRC x11 1.0-6.0 s
(1,4)
1.0-6.0 s
(1,4)
1.0-6.0 s
(1,4)
1.0-6.0 s
(1,4)
1.0-6.0 s
(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 1.6 s for VDD.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the F
RC clock source is only recommended if the
conversion will be performed during Sleep.
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9
Set GO/DONE bit
Holding Capacitor is Disconnected from Analog Input (typically 100 ns)
b7 b6 b5 b4 b3 b2 b1 b0
Tcy to TAD
Conversion Starts
ADRES register is loaded,
GO/DONE
bit is cleared,
ADIF bit is set,
Holding capacitor is connected to analog input
T
AD0