Datasheet

 2010-2012 Microchip Technology Inc. DS41417B-page 215
PIC16(L)F722A/723A
FIGURE 23-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS
VBOR
VDD
(Device in Brown-out Reset) (Device not in Brown-out Reset)
33
(1)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. 2 ms delay if
PWRTE
= 0 and VREGEN = 1.
Reset
(due to BOR)
VBOR and VHYST
37