Datasheet

PIC16(L)F722A/723A
DS41417B-page 214  2010-2012 Microchip Technology Inc.
TABLE 23-3: CLKOUT AND I/O TIMING PARAMETERS
FIGURE 23-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C T
A +125°C
Param
No.
Sym. Characteristic Min. Typ† Max. Units Conditions
OS11 TosH2ckL Fosc to CLKOUT
(1)
——70nsVDD = 3.3-5.0V
OS12 TosH2ckH Fosc to CLKOUT
(1)
——72nsVDD = 3.3-5.0V
OS13 TckL2ioV CLKOUT to Port out valid
(1)
——20ns
OS14 TioV2ckH Port input valid before CLKOUT
(1)
TOSC + 200 ns — — ns
OS15 TosH2ioV Fosc (Q1 cycle) to Port out valid — 50 70* ns VDD = 3.3-5.0V
OS16 TosH2ioI Fosc (Q2 cycle) to Port input invalid
(I/O in hold time)
50 — — ns VDD = 3.3-5.0V
OS17 TioV2osH Port input valid to Fosc(Q2 cycle)
(I/O in setup time)
20 — — ns
OS18 TioR Port output rise time
(2)
—
—
40
15
72
32
ns VDD = 2.0V
V
DD = 3.3-5.0V
OS19 TioF Port output fall time
(2)
—
—
28
15
55
30
ns VDD = 2.0V
V
DD = 3.3-5.0V
OS20* Tinp INT pin input high or low time 25 — — ns
OS21* Trbp PORTB interrupt-on-change new input
level time
T
CY ——ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25C unless otherwise stated.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x T
OSC.
2: Includes OSC2 in CLKOUT mode.
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Start-Up Time
Internal Reset
(1)
Watchdog Timer
33
32
30
31
34
I/O pins
34
Note 1: Asserted low.
Reset
(1)