Datasheet

 2010-2012 Microchip Technology Inc. DS41417B-page 171
PIC16(L)F722A/723A
FIGURE 17-13: I
2
C SLAVE MODE TIMING (TRANSMISSION 10-BIT ADDRESS)
SDA SCL SSPIF BF
S
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9
P
1 1 1 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 1 1 1 0 A8
R/W = 1
ACK
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
Bus Master
sends Stop condition
A9
6
Receive Second Byte of Address
Cleared by hardware when SSPADD is updated with low byte of address.
UA
Clock is held low until update of SSPADD has taken place
UA is set indicating that the SSPADD needs to be updated
UA is set indicating that SSPADD needs to be updated
Cleared by hardware when SSPADD is updated with high byte of address.
SSPBUF is written with contents of SSPSR
Dummy read of SSPBUF to clear BF flag
Receive First Byte of Address
1 2 3 4 5 7 8 9
D7 D6 D5 D4 D3 D1
ACK
D2
6
Transmitting Data Byte
D0
Dummy read of SSPBUF to clear BF flag
Sr
Cleared in software
Write of SSPBUF
Cleared in software
Completion of clears BF flag
CKP
CKP is set in software, initiates transmission
CKP is automatically cleared in hardware holding SCL low
Clock is held low until
update of SSPADD has
taken place
data transmission
Clock is held low until CKP is set to ‘1’
Bus Master sends Restarts condition
Dummy read of SSPBUF to clear BF flag