PIC16(L)F720/721 20-Pin Flash Microcontrollers Devices Included In This Data Sheet: • PIC16F720 • PIC16LF720 • PIC16F721 • PIC16LF721 High-Performance RISC CPU: • Only 35 Instructions to Learn: - All single-cycle instructions except branches • Operating Speed: - DC – 16 MHz oscillator/clock input - DC – 250 ns instruction cycle • Up to 4K x 14 Words of Flash Program Memory • Up to 256 bytes of Data Memory (RAM) • Interrupt Capability • 8-Level Deep Hardware Stack • Direct, Indirect and Relative Addressi
PIC16(L)F720/721 DS40001430E-page 2 Debug(1) XLP PIC16(L)F707 (1) 8192 363 36 14 32 4/2 1 1 PIC16(L)F720 (2) 2048 128 18 12 — 2/1 1 1 PIC16(L)F721 (2) 4096 256 18 12 — 2/1 1 1 PIC16(L)F722 (4) 2048 128 25 11 8 2/1 1 1 PIC16(L)F722A (3) 2048 128 25 11 8 2/1 1 1 PIC16(L)F723 (4) 4096 192 25 11 8 2/1 1 1 PIC16(L)F723A (3) 4096 192 25 11 8 2/1 1 1 PIC16(L)F724 (4) 4096 192 36 14 16 2/1 1 1 PIC16(L)F726 (4) 8192 368 25 11 8 2/1 1 1 PIC16(L)F727 (4) 8192 368 36 14 16 2/1 1 1 Note 1: I - Debugging, Integrated
PIC16(L)F720/721 Pin Diagrams – 20-PIN DIAGRAM FOR PIC16F720/721 AND PIC16LF720/721 PDIP, SOIC, SSOP VDD 1 20 VSS 2 19 RA0/AN0/ICSPDAT 3 18 RA1/AN1/ICSPCLK RA3/MCLR/VPP 4 17 RA2/AN2/T0CKI/INT 16 RC0/AN4 15 RC1/AN5 14 RC2/AN6 13 RB4/AN10/SDI/SDA RC5/CCP1 5 PIC16F720/721 PIC16LF720/721 RA5/T1CKI/CLKIN RA4/AN3/T1G/CLKOUT RC4 6 RC3/AN7 7 RC6/AN8/SS 8 RC7/AN9/SDO 9 12 RB5/AN11/RX/DT 10 11 RB6/SCK/SCL RB7/TX/CK Pin Diagrams – 20-PIN DIAGRAM FOR PIC16F720/721 AND PIC16LF720/7
PIC16(L)F720/721 CCP AUSART SSP Interrupt Pull-up 19 16 AN0 — — — — IOC Y ICSPDAT RA1 18 15 AN1 — — — — IOC Y ICSPCLK RA2 17 14 AN2 T0CKI — — — INT/IOC — — RA3 4 1 — — — — — IOC Y MCLR/VPP Basic Timers RA0 I/O A/D 20-Pin QFN 20-PIN ALLOCATION TABLE (PIC16F720/721 AND PIC16LF720/721) 20-Pin PDIP/SOIC/ SSOP TABLE 1: RA4 3 20 AN3 T1G — — — IOC Y CLKOUT RA5 2 19 — T1CKI — — — IOC Y CLKIN RB4 13 10 AN10 — — — SDI/SDA IOC Y —
PIC16(L)F720/721 Table of Contents 1.0 Device Overview ......................................................................................................................................................................... 7 2.0 Memory Organization ................................................................................................................................................................ 11 3.0 Resets ......................................................................................
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PIC16(L)F720/721 1.0 DEVICE OVERVIEW The PIC16(L)F720/721 devices are covered by this data sheet. They are available in 20-pin packages. Figure 1-1 shows a block diagram of the PIC16(L)F720/721 devices. Table 1-1 shows the pinout descriptions. 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 FIGURE 1-1: 20-PIN DEVICE BLOCK DIAGRAM FOR PIC16F720/721 PORTA Configuration 13 Program Counter Flash Program 8K x 14 (1) Memory Program Program Bus RAM File Registers Registers(1) 368 x 8 8 Level Stack (13-bit) Memory 14 RA0 RA1 RA2 RA3 RA4 RA5 8 Data Bus RAM Addr PORTB 9 Addr MUX Instruction Instruction Reg reg 7 Direct Addr 8 RB4 RB5 RB6 RB7 Indirect Addr FSR FSR Reg reg STATUS STATUS Reg reg 8 3 CLKIN CLKOUT Instruction Decode & Control Timing Generation MUX P
PIC16(L)F720/721 TABLE 1-1: PINOUT DESCRIPTION Name RA0/AN0/ICSPDAT/ICDDAT RA1/AN1/ICSPCLK/ICDCLK RA2/AN2/T0CKI/INT RA3/MCLR/VPP RA4/AN3/T1G/CLKOUT Function OUT RA0 TTL CMOS AN0 AN — ICSPDAT ST CMOS ICSP™ Data I/O. General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. RA1 TTL CMOS AN1 AN — ICSPCLK ST — RB4/AN10/SDI/SDA RB5/AN11/RX/DT RB6/SCK/SCL RB7/TX/CK RC0/AN4 RC1/AN5 RC2/AN6 RC3/AN7 Legend: General purpose I/O.
PIC16(L)F720/721 TABLE 1-1: PINOUT DESCRIPTION (CONTINUED) Name Function IN OUT RC4 RC4 ST CMOS General purpose I/O. RC5/CCP1 RC5 ST CMOS General purpose I/O. CCP1 ST CMOS Capture/Compare/PWM 1. RC6 ST CMOS General purpose I/O. AN8 AN — A/D Channel 8 Input. RC6/AN8/SS RC7/AN9/SDO VDD Vss Legend: Description SS ST — RC7 ST CMOS General purpose I/O. AN9 AN — A/D Channel 9 Input. Slave Select input. SDO — CMOS VDD Power — Positive supply. SPI Data Output.
PIC16(L)F720/721 2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization The PIC16(L)F720/721 has a 13-bit program counter capable of addressing a 8K x 14 program memory space. Table 2-1 shows the memory sizes implemented. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h.
PIC16(L)F720/721 2.2 Data Memory Organization The data memory is partitioned into multiple banks which contain the General Purpose Registers (GPRs) and the Special Function Registers (SFRs). Bits RP0 and RP1 are bank select bits. RP1 RP0 0 0 Bank 0 is selected 0 1 Bank 1 is selected 1 0 Bank 2 is selected 1 1 Bank 3 is selected Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers.
PIC16(L)F720/721 2.2.1 GENERAL PURPOSE REGISTER FILE The register file is organized as 128 x 8 bits in the PIC16(L)F720, 256 x 8 bits in the PIC16(L)F721. Each register is accessed either directly or indirectly through the File Select Register (FSR), (Refer to Section 2.5 “Indirect Addressing, INDF and FSR Registers”). 2.2.
PIC16(L)F720/721 FIGURE 2-3: PIC16(L)F720 SPECIAL FUNCTION REGISTERS File Address INDF(*) 00h INDF(*) 80h INDF(*) 100h INDF(*) 180h TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 104h FSR 04h FSR 84h 05h TRISA 85h 105h FSR ANSELA 184h PORTA PORTB 06h TRISB 86h 106h ANSELB 186h PORTC 07h TRISC 87h 107h ANSELC 187h 08h 88h 108h 09h 89h 109h 185h 188h 189h P
PIC16(L)F720/721 FIGURE 2-4: PIC16(L)F721 SPECIAL FUNCTION REGISTERS File Address INDF(*) 00h INDF(*) 80h INDF(*) 100h INDF(*) 180h TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 104h FSR 04h FSR 84h 05h TRISA 85h 105h FSR ANSELA 184h PORTA PORTB 06h TRISB 86h 106h ANSELB 186h PORTC 07h TRISC 87h 107h ANSELC 187h 88h 108h 08h 09h PCLATH 89h 188h 109h 10Ah 1
PIC16(L)F720/721 TABLE 2-2: Address SPECIAL FUNCTION REGISTER SUMMARY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 0 00h( 2) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 01h TMR0 Timer0 module Register xxxx xxxx uuuu uuuu 02h( 2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 03h( 2) STATUS 000q quuu 04h( 2) FSR 05h PORTA I
PIC16(L)F720/721 TABLE 2-2: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 1 80h( 2) INDF 81h OPTION_ REG 82h( 2) PCL 83h( 2) STATUS 84h( 2) FSR 85h(5) TRISA 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 1111 ---- 87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 88h — Unimplemented — — 89h — Unimplem
PIC16(L)F720/721 TABLE 2-2: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 2 100h( 2) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 101h TMR0 Timer0 module Register xxxx xxxx uuuu uuuu 102h( 2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 103h( 2) STATUS 0001 1xxx 000q quuu
PIC16(L)F720/721 TABLE 2-2: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 3 180h( 2) INDF 181h OPTION_ REG 182h( 2) PCL 183h( 2) STATUS Addressing this location uses contents of FSR to address data memory (not a physical register) RABPU INTEDG IRP RP1 RP0 — — — ANSA4 T0CS T0SE PSA xxxx xxxx xxxx xxxx PS1 PS0 1111 1111 1111 1111 0000 0000 0000 0000 Z DC C 00
PIC16(L)F720/721 2.2.2.1 STATUS Register The STATUS register, shown in Register 2-1, contains: • the arithmetic status of the ALU • the Reset status • the bank select bits for data memory (SRAM) The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
PIC16(L)F720/721 2.2.2.2 OPTION_REG Register Note: The OPTION_REG register, shown in Register 2-2, is a readable and writable register, which contains various control bits to configure: • Software programmable prescaler for the Timer0/ WDT • External RA2/INT interrupt • Timer0 • Weak pull-ups on PORTA or PORTB REGISTER 2-2: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting the PSA bit of the OPTION_REG register to ‘1’. Refer to Section 12.1.
PIC16(L)F720/721 2.2.2.3 PCON Register The Power Control (PCON) register contains flag bits (refer to Table 3-4) to differentiate between a: • • • • Power-on Reset (POR) Brown-out Reset (BOR) Watchdog Timer Reset (WDT) External MCLR Reset The PCON register also controls the software enable of the BOR. The PCON register bits are shown in Register 2-3.
PIC16(L)F720/721 2.3 PCL and PCLATH The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in Figure 2-5 shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH).
PIC16(L)F720/721 2.5 Indirect Addressing, INDF and FSR Registers EXAMPLE 2-2: INDIRECT ADDRESSING MOVLW 020h ;initialize pointer MOVWF FSR ;to RAM BANKISEL 020h NEXT CLRF INDF ;clear INDF register INCF FSR ;inc pointer BTFSS FSR,4 ;all done? GOTO NEXT ;no clear next CONTINUE ;yes continue The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register.
PIC16(L)F720/721 3.0 RESETS The PIC16(L)F720/721 differentiates between various kinds of Reset: a) b) c) d) e) f) Power-on Reset (POR) WDT Reset during normal operation WDT Reset during Sleep MCLR Reset during normal operation MCLR Reset during Sleep Brown-out Reset (BOR) A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 3-1. Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset.
PIC16(L)F720/721 TABLE 3-1: STATUS BITS AND THEIR SIGNIFICANCE POR BOR TO PD 0 x 1 1 Power-on Reset or LDO Reset 0 x 0 x Illegal, TO is set on POR 0 x x 0 Illegal, PD is set on POR 1 0 1 1 Brown-out Reset 1 1 0 1 WDT Reset 1 1 0 0 WDT Wake-up 1 1 u u MCLR Reset during normal operation 1 1 1 0 MCLR Reset during Sleep or interrupt wake-up from Sleep TABLE 3-2: Condition RESET CONDITION FOR SPECIAL REGISTERS(2) Program Counter STATUS Register PCON Register Pow
PIC16(L)F720/721 3.1 MCLR 3.3 The PIC16(L)F720/721 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a Reset does not drive the MCLR pin low. Voltages applied to the pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD.
PIC16(L)F720/721 3.4.2 WDT CONTROL The WDTEN bit is located in the Configuration Word Register 1. When set, the WDT runs continuously. The PSA and PS<2:0> bits of the OPTION_REG register control the WDT period. See Section 12.0 “Timer0 Module” for more information.
PIC16(L)F720/721 3.5 Brown-out Reset (BOR) Brown-out Reset is enabled by programming the BOREN<1:0> bits in the Configuration register. Between the POR and BOR, complete voltage range coverage for execution protection can be implemented. Two bits are used to enable the BOR. When BOREN = 11, the BOR is always enabled. When BOREN = 10, the BOR is enabled, but disabled during Sleep. When BOREN = 0X, the BOR is disabled. If VDD falls below VBOR for greater than parameter (TBOR) (see Section 23.
PIC16(L)F720/721 3.6 Time-out Sequence 3.7 PWRT time-out is invoked after POR has expired. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit = 1 (PWRT disabled), there will be no timeout at all. Figure 3-5, Figure 3-6 and Figure 3-7 depict time-out sequences. Power Control (PCON) Register The Power Control (PCON) register has two Status bits to indicate what type of Reset that last occurred. Bit 0 is BOR (Brown-out Reset).
PIC16(L)F720/721 FIGURE 3-6: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2 VDD MCLR Internal POR TPWRT PWRT Time-out Internal Reset FIGURE 3-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD): CASE 3 VDD MCLR Internal POR TPWRT PWRT Time-out Internal Reset 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 TABLE 3-6: Register INITIALIZATION CONDITION FOR REGISTERS Address Power-on Reset/ Brown-out Reset(1) MCLR Reset/ WDT Reset W Wake-up from Sleep through Interrupt/Time-out — xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h/80h/ 100h/180h xxxx xxxx xxxx xxxx uuuu uuuu TMR0 01h/101h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h/ 102h/182h 0000 0000 0000 0000 PC + 1(3) STATUS 03h/83h/ 103h/183h 0001 1xxx 000q quuu(4) uuuq quuu(4) FSR 04h/84h/ 104h/184h xxxx xxxx uuuu uuuu u
PIC16(L)F720/721 TABLE 3-6: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED) Address Power-on Reset/ Brown-out Reset(1) PCON 8Eh ---- --qq ---- --uu(1,5) ---- --uu T1GCON 8Fh 0000 0x00 uuuu uxuu uuuu uxuu OSCCON 90h --10 qq-- --10 qq-- --uu qq-- OSCTUNE 91h --00 0000 --uu uuuu --uu uuuu PR2 92h 1111 1111 1111 1111 uuuu uuuu SSPADD 93h 0000 0000 0000 0000 uuuu uuuu SSPMSK 93h 1111 1111 1111 1111 uuuu uuuu SSPSTAT 94h 0000 0000 0000 0000 uuuu uuuu WPUB 115h 1111
PIC16(L)F720/721 TABLE 3-7: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Program Counter STATUS Register PCON Register Power-on Reset 0000h 0001 1xxx ---- --0x MCLR Reset during normal operation 0000h 000u uuuu ---- --uu MCLR Reset during Sleep 0000h 0001 0uuu ---- --uu WDT Reset 0000h 0000 uuuu ---- --uu WDT Wake-up PC + 1 uuu0 0uuu ---- --uu Brown-out Reset 0000h 0001 1xxx ---- --10 uuu1 0uuu ---- --uu Condition Interrupt Wake-up from Sleep PC + 1 (1) Legend: u = unchan
PIC16(L)F720/721 4.0 INTERRUPTS The PIC16(L)F720/721 device family features an interruptible core, allowing certain events to preempt normal program flow. An Interrupt Service Routine (ISR) is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode.
PIC16(L)F720/721 4.1 Operation interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its Interrupt Flag, but will not cause the processor to redirect to the interrupt vector. Interrupts are disabled upon any device Reset.
PIC16(L)F720/721 4.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction.
PIC16(L)F720/721 4.5.1 INTCON REGISTER Note: The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, PORTB change and external RA2/INT pin interrupts. REGISTER 4-1: R/W-0 INTCON: INTERRUPT CONTROL REGISTER R/W-0 GIE Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE of the INTCON register.
PIC16(L)F720/721 4.5.2 PIE1 REGISTER The PIE1 register contains the interrupt enable bits, as shown in Register 4-2. REGISTER 4-2: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
PIC16(L)F720/721 4.5.3 PIR1 REGISTER The PIR1 register contains the interrupt flag bits, as shown in Register 4-3. REGISTER 4-3: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16(L)F720/721 TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 38 RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 21 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 39 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 40 Name INTCON OPTION_REG Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown.
PIC16(L)F720/721 NOTES: DS40001430E-page 42 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 5.0 LOW DROPOUT (LDO) VOLTAGE REGULATOR The PIC16F720/721 devices differ from the PIC16LF720/721 devices due to an internal Low Dropout (LDO) voltage regulator. The PIC16F720/721 contain an internal LDO, while the PIC16LF720/721 do not. The lithography of the die allows a maximum operating voltage of 3.6V on the internal digital logic. In order to continue to support 5.0V designs, a LDO voltage regulator is integrated on the die.
PIC16(L)F720/721 NOTES: DS40001430E-page 44 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 6.0 I/O PORTS 6.1.1 WEAK PULL-UPS There are as many as eighteen general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. Each of the PORTA pins has an individually configurable internal weak pull-up. Control bits WPUA<5:0> enable or disable each pull-up (see Register 6-5).
PIC16(L)F720/721 REGISTER 6-1: PORTA: PORTA REGISTER U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — RA5 RA4 RA3(1) RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RA<5:0>: PORTA I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: x = Bit is unknown RA<3> is input only.
PIC16(L)F720/721 REGISTER 6-4: IOCA: INTERRUPT-ON-CHANGE PORTA REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCA<5:0>: Interrupt-on-Change PORTA Control bits 1 = Interrupt-on-change enabled(1) 0 = Interrupt-on-change disabled x = Bit is unknown
PIC16(L)F720/721 6.1.4 PIN DESCRIPTIONS AND DIAGRAMS Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the A/D Converter (ADC), refer to the appropriate section in this data sheet. 6.1.4.1 RA0/AN0/ICSPDAT Figure 6-1 shows the diagram for this pin.
PIC16(L)F720/721 FIGURE 6-1: BLOCK DIAGRAM OF RA0 ICSP™ mode Analog(1) Input mode DEBUG VDD Data Bus D Weak Q CK Q WR WPUA RABPU RD WPUA VDD PORT_ICDDAT 0 1 D WR PORTA Q 1 0 CK Q I/O Pin VSS 0 1 D WR TRISA TRIS_ICDDAT Q CK Q RD TRISA Analog(1) Input mode RD PORTA D WR IOCA Q CK Q Q RD IOCA D EN Q Q3 D EN Interrupt-on-Change RD PORTA ICSPDAT To A/D Converter Note 1: ANSEL determines Analog Input mode. 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 FIGURE 6-2: BLOCK DIAGRAM OF RA1 Data Bus WR WPUA D Q DEBUG VDD CK Q Weak RABPU RD WPUA D WR PORTA ICSP™ mode Analog(1) Input mode Q PORT_ICDCLK CK Q VDD 0 1 1 0 D WR TRISA I/O Pin Q 0 CK Q VSS 1 RD TRISA Analog(1) Input mode TRIS_ICDCLK RD PORTA D WR IOCA Q Q CK Q D EN Q3 RD IOCA Q Interrupt-on-Change D EN RD PORTA To A/D Converter ICSPCLK Note DS40001430E-page 50 1: ANSEL determines Analog Input mode. 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 FIGURE 6-3: BLOCK DIAGRAM OF RA2 Data Bus WR WPUA D CK Q Analog(1) Input mode Q Weak To Voltage Regulator (for PIC16F720/721 only) RABPU RD WPUA D WR PORTA VDD CK VDD Q Q I/O Pin D WR TRISA CK Q Q VSS Analog(1) Input mode RD TRISA RD PORTA D WR IOCA CK Q Q Q D EN RD IOCA Q Interrupt-onChange Q3 D EN RD PORTA To Timer0 To INT To A/D Converter Note 1: ANSEL determines Analog Input mode. 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 FIGURE 6-4: BLOCK DIAGRAM OF RA3 FIGURE 6-5: BLOCK DIAGRAM OF RA4 VDD MCLRE Analog(2) Input mode Weak Data Bus Data Bus Reset RD TRISA Input Pin WR WPUA D CK Q VDD Q Weak VSS MCLRE RD PORTA D WR IOCA MCLRE CK VSS RABPU RD WPUA Q Q Q RD IOCA Interrupt-onChange Q D Q3 D WR PORTA CK FOSC/4 Q 0 I/O Pin CLKOUT Enable D WR TRISA 1 Q EN RD PORTA VDD CLKOUT Enable D EN CLK modes CK VSS Q INTOSC/ RC/EC(1) Q CLKOUT Enable RD TRISA Analog Input mod
PIC16(L)F720/721 FIGURE 6-6: BLOCK DIAGRAM OF RA5 INTOSC mode Data Bus D WR WPUA CK VDD Q Weak Q RABPU RD WPUA D WR PORTA CK VDD Q Q I/O Pin D WR TRISA CK Q Q VSS INTOSC mode RD TRISA RD PORTA D WR IOCA CK Q Q Q D EN Q3 RD IOCA Q D EN Interrupt-onChange RD PORTA To TMR1 or CLKIN TABLE 6-1: Name ANSELA OPTION_REG SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — ANSA4 — ANSA2 ANSA1 ANSA0 47 RABPU
PIC16(L)F720/721 6.2 PORTB and TRISB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 6-7). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16(L)F720/721 REGISTER 6-6: PORTB: PORTB REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u U-0 U-0 U-0 U-0 RB7 RB6 RB5 RB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 RB<7:4>: PORTB I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL bit 3-0 Unimplemented: Read as ‘0’ REGISTER 6-7: x = Bit is unknown TRISB: PORTB TRI-STATE REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-
PIC16(L)F720/721 REGISTER 6-9: R/W-0 IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER R/W-0 IOCB7 IOCB6 R/W-0 IOCB5 R/W-0 U-0 U-0 U-0 U-0 IOCB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 IOCB<7:4>: Interrupt-on-Change PORTB Control bits 1 = Interrupt-on-change enabled(1) 0 = Interrupt-on-change disabled bit 3-0 Unimplemented: Read as ‘0’ x = Bit is unknown Note 1: Interru
PIC16(L)F720/721 6.2.4 PIN DESCRIPTIONS AND DIAGRAMS Each PORTB pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the SSP, I2C™ or interrupts, refer to the appropriate section in this data sheet. 6.2.4.1 RB4/AN10/SDI/SDA Figure 6-7 shows the diagram for this pin. The RB4 pin is configurable to function as one of the following: FIGURE 6-7: Data Bus WR WPUB WR PORTB 6.2.4.
PIC16(L)F720/721 FIGURE 6-8: Data Bus WR WPUB D BLOCK DIAGRAM OF RB5 Q Analog(1) Input mode Data Bus VDD CK Q WR WPUB Weak D BLOCK DIAGRAM OF RB6 Q VDD CK Q Weak RABPU RD WPUB RABPU RD WPUB FIGURE 6-9: SYNC SPEN D WR PORTB Q CK Q D VDD AUSART DT 1 0 1 0 D WR TRISB Q WR TRISB VSS 0 1 Analog(1) Input mode RD TRISB CK Q Q CK Q RD IOCB Q WR IOCB D EN D 0 1 From SSP 1 0 I/O Pin VSS 1 0 Q Q CK Q D EN Q3 ST EN Interrupt-onChange Q VDD RD PORTB D D Q SSPEN SSP Cloc
PIC16(L)F720/721 FIGURE 6-10: Data Bus D WR WPUB BLOCK DIAGRAM OF RB7 Q VDD CK Q Weak RABPU RD WPUB SPEN TXEN SYNC D WR PORTB Q AUSART CK 0 1 AUSART TX 1 0 VDD CK Q 0 1 0 1 D WR TRISB I/O Pin Q ‘1’ CK Q 0 1 VSS 1 0 RD TRISB RD PORTB D WR IOCB Q Q CK Q D EN RD IOCB Q Q3 D EN Interrupt-onChange RD PORTB TABLE 6-2: Name ANSELB SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — ANSB5 ANSB4 — — — — 56
PIC16(L)F720/721 6.3 PORTC and TRISC Registers PORTC is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISC (Register 6-12). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16(L)F720/721 REGISTER 6-12: TRISC: PORTC TRI-STATE REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown TRISC<7:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output REGISTER 6-13:
PIC16(L)F720/721 6.3.2 RC0/AN4 Figure 6-11 shows the diagram for this pin. The RC0 pin is configurable to function as one of the following: FIGURE 6-11: Data Bus • General purpose I/O • Analog input for the A/D 6.3.3 RC1/AN5 D WR PORTC Figure 6-11 shows the diagram for this pin. The RC1 pin is configurable to function as one of the following: • General purpose I/O • Analog input for the A/D 6.3.4 RC2/AN6 Figure 6-12 shows the diagram for this pin.
PIC16(L)F720/721 FIGURE 6-13: BLOCK DIAGRAM OF RC4 FIGURE 6-15: Data Bus VDD D I/O Pin Data Bus D WR PORTC Q CK Q D WR TRISC WR PORTC CK D WR TRISC Q CK Q CK Q Q Q VSS Analog Input mode(1) RD TRISC RD PORTC To SS Input RD PORTC To A/D Converter FIGURE 6-14: Data bus BLOCK DIAGRAM OF RC5 CCP1OUT Enable D CK CCP1OUT D CK 1: ANSEL determines Analog Input mode.
PIC16(L)F720/721 TABLE 6-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELC ANSC7 ANSC6 — — ANSC3 ANSC2 ANSC1 ANSC0 61 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 61 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 60 Name Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC. DS40001430E-page 64 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 7.0 OSCILLATOR MODULE 7.1 Overview Clock source modes are configured by the FOSC bits in Configuration Word 1 (CONFIG1). The oscillator module can be configured for one of the following modes of operation. The oscillator module has a variety of clock sources and selection features that allow it to be used in a range of applications while maximizing performance and minimizing power consumption. Figure 7-1 illustrates a block diagram of the oscillator module. 1. 2. 3.
PIC16(L)F720/721 7.2 Clock Source Modes Clock source modes can be classified as external or internal. • Internal clock source (INTOSC) is contained within the oscillator module and derived from a 500 kHz high precision oscillator. The oscillator module has eight selectable output frequencies, with a maximum internal frequency of 16 MHz. • The External Clock mode (EC) relies on an external signal for the clock source.
PIC16(L)F720/721 7.4 Oscillator Control The Oscillator Control (OSCCON) register (Figure 7-1) displays the status and allows frequency selection of the internal oscillator (INTOSC) system clock.
PIC16(L)F720/721 7.5 Oscillator Tuning The INTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 7-2). The default value of the OSCTUNE register is ‘0’. The value is a 6-bit two’s complement number. When the OSCTUNE register is modified, the INTOSC frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred.
PIC16(L)F720/721 7.6 External Clock Modes 7.6.1 EC MODE The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to the CLKIN input and the CLKOUT is available for general purpose I/O. Figure 7-2 shows the pin connections for EC mode. FIGURE 7-2: EXTERNAL CLOCK (EC) MODE OPERATION CLKIN Clock from Ext.
PIC16(L)F720/721 NOTES: DS40001430E-page 70 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 8.0 DEVICE CONFIGURATION Device configuration consists of Configuration Word 1 and Configuration Word 2 registers, code protection and Device ID. 8.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 register at 2007h and Configuration Word 2 register at 2008h. These registers are only accessible during programming. 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 REGISTER 8-1: CONFIGURATION WORD 1 U-1 R/P-1 U-1 U-1 R/P-1 R/P-1 — PLLEN — — BOREN1 BOREN0 bit 13 bit 8 U-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1 R/P-1 R/P-1 — CP MCLRE PWRTE WDTEN — FOSC1 FOSC0 bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 13 Unimplemented: Read as ‘1’ bit 12 PLLEN: INTOSC PLL Enable bit 0 = INTOSC
PIC16(L)F720/721 REGISTER 8-2: CONFIGURATION WORD 2 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — bit 13 bit 8 U-1 U-1 U-1 Reserved U-1 U-1 R/P-1 R/P-1 — — — — — — WRT1 WRT0 bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 13-5 Unimplemented: Read as ‘1’ bit 4 Reserved: Maintain as ‘1’ bit 3-2 Unimplemented: Read as ‘1’ bit 1-0 WRT<1:0>: Flash Memory
PIC16(L)F720/721 8.2 Code Protection If the code protection bit(s) have not been programmed, the on-chip program memory can be read out using ICSP™ for verification purposes. Note: 8.3 The entire Flash program memory will be erased when the code protection is turned off. See the “PIC16(L)F720/721 Memory Programming Specification” (DS41409) for more information.
PIC16(L)F720/721 9.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 8-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 8-bit binary result via successive approximation and stores the conversion result into the ADC result register (ADRES).
PIC16(L)F720/721 9.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • 9.1.3 Port configuration Channel selection ADC conversion clock source Interrupt control 9.1.1 When converting analog signals, the I/O pin selected as the input channel should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 6.0 “I/O Ports” for more information.
PIC16(L)F720/721 FIGURE 9-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES TCY to TAD TAD0 TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 b7 b6 b5 b4 b3 b2 b1 b0 Conversion Starts Holding Capacitor is disconnected from Analog Input (typically 100 ns) Set GO/DONE bit 9.1.4 INTERRUPTS The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register.
PIC16(L)F720/721 9.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. When the FRC clock source is selected, the ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes.
PIC16(L)F720/721 9.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC.
PIC16(L)F720/721 REGISTER 9-2: ADCON1: A/D CONTROL REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — ADCS2 ADCS1 ADCS0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC (clock supplied from a dedicated RC oscillator) 100 = FOSC/4 101 = FOSC/16
PIC16(L)F720/721 9.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 9-3. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 9-3.
PIC16(L)F720/721 Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. FIGURE 9-3: ANALOG INPUT MODEL VDD Rs VA VT 0.6V ANx CPIN 5 pF VT 0.
PIC16(L)F720/721 TABLE 9-2: SUMMARY OF ASSOCIATED ADC REGISTERS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/ DONE ADON 79 ADCON1 — ADCS2 ADCS1 ADCS0 — — — — 80 ANSELA — — ANSA5 ANSA4 — ANSA2 ANSA1 ANSA0 47 Name ANSELB — — ANSB5 ANSB4 — — — — 56 ANSELC ANSC7 ANSC6 — — ANSC3 ANSC2 ANSC1 ANSC0 61 FVRRDY FVREN TSEN TSRNG — — ADFVR1 ADFVR0 86 ADRES FVRCON INTCON ADC Result Register 80 G
PIC16(L)F720/721 NOTES: DS40001430E-page 84 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 10.0 FIXED VOLTAGE REFERENCE This device contains an internal voltage regulator. To provide a reference for the regulator, a fixed voltage reference is provided. This fixed voltage is also user accessible via an A/D converter channel. User level fixed voltage functions are controlled by the FVRCON register, which is shown in Register 10-1. FIGURE 10-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> 2 x1 x2 x4 FVR (To ADC Module) 1.
PIC16(L)F720/721 REGISTER 10-1: FVRCON: FIXED VOLTAGE REFERENCE REGISTER R-q R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 FVRRDY FVREN TSEN TSRNG — — ADFVR1 ADFVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown q = Value depends on condition bit 7 FVRRDY(1): Fixed Voltage Reference Ready Flag bit 0 = Fixed Voltage Reference output is not active or stable 1 = Fixed Voltage
PIC16(L)F720/721 11.0 TEMPERATURE INDICATOR MODULE FIGURE 11-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit’s range of operating temperature falls between -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC.
PIC16(L)F720/721 NOTES: DS40001430E-page 88 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 12.0 TIMER0 MODULE 12.1.1 The Timer0 module will increment every instruction cycle, if used without a prescaler. 8-Bit Timer mode is selected by clearing the T0CS bit of the OPTION_REG register.
PIC16(L)F720/721 12.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION_REG register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’. There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256.
PIC16(L)F720/721 12.
PIC16(L)F720/721 NOTES: DS40001430E-page 92 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 13.0 TIMER1 MODULE WITH GATE CONTROL • • • • The Timer1 module is a 16-bit timer/counter with the following features: Figure 13-1 is a block diagram of the Timer1 module.
PIC16(L)F720/721 13.1 Timer1 Operation 13.2 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source.
PIC16(L)F720/721 13.3 Timer1 Prescaler 13.5 Timer1 Gate Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry. This is also referred to as Timer1 gate count enable.
PIC16(L)F720/721 13.5.2.1 T1G Pin Gate Operation 13.5.2.4 The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 gate circuitry. 13.5.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-tohigh pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. 13.5.2.3 Timer2 Match Gate Operation The TMR2 register will increment until it matches the value in the PR2 register.
PIC16(L)F720/721 13.5.3 TIMER1 GATE TOGGLE MODE When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate signal, as opposed to the duration of a single level pulse. The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure 13-4 for timing details. Timer1 Gate Toggle mode is enabled by setting the T1GTM bit of the T1GCON register.
PIC16(L)F720/721 13.6 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • • • • TMR1ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. Note: 13.
PIC16(L)F720/721 FIGURE 13-3: TIMER1 GATE COUNT ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL TIMER1 N FIGURE 13-4: N+1 N+2 N+3 N+4 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL TIMER1 N 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 FIGURE 13-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 TMR1GIF DS40001430E-page 100 N Cleared by software N+1 N+2 Set by hardware on falling edge of T1GVAL Cleared by software 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 FIGURE 13-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 TMR1GIF N Cleared by software 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 13.10 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register 13-1, is used to control Timer1 and select the various features of the Timer1 module.
PIC16(L)F720/721 13.11 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), shown in Register 13-2, is used to control Timer1 gate.
PIC16(L)F720/721 TABLE 13-6: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 ANSELB — — ANSB5 ANSB4 CCP1CON — — DC1 B1 INTCON Bit 3 Bit 2 Bit 1 Bit 0 — — — — CCP1M3 CCP1M2 CCP1M1 CCP1M0 Register on Page 56 107 GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 38 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 39 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 40 RB7 RB6 RB5 RB4 — — — — 55 PORTB TMR1H Holding R
PIC16(L)F720/721 14.0 TIMER2 MODULE The Timer2 module is an 8-bit timer with the following features: • • • • • 8-bit timer register (TMR2) 8-bit period register (PR2) Interrupt on TMR2 match with PR2 Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘1’. Timer2 is turned off by clearing the TMR2ON bit to a ‘0’. The Timer2 prescaler is controlled by the T2CKPS bits in the T2CON register.
PIC16(L)F720/721 14.
PIC16(L)F720/721 15.0 CAPTURE/COMPARE/PWM (CCP) MODULE TABLE 15-1: The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate a Pulse-Width Modulated signal of varying frequency and duty cycle.
PIC16(L)F720/721 15.1 Capture Mode 15.1.3 In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin CCP1. An event is defined as one of the following and is configured by the CCP1M<3:0> bits of the CCP1CON register: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge 15.1.1 CCP1 PIN CONFIGURATION In Capture mode, the CCP1 pin should be configured as an input by setting the associated TRIS control bit.
PIC16(L)F720/721 TABLE 15-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELB — — ANSB5 ANSB4 — — — — 56 CCP1CON — — DC1 B1 Name CCPR1L CCP1M3 CCP1M2 CCP1M1 CCP1M0 Capture/Compare/PWM Register Low Byte CCPR1H 107 — Capture/Compare/PWM Register High Byte — GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 38 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 39 PIR1 TMR1GIF ADIF RCIF TXI
PIC16(L)F720/721 15.2 Compare Mode 15.2.2 In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCP1 module may: • • • • • Toggle the CCP1 output Set the CCP1 output Clear the CCP1 output Generate a Special Event Trigger Generate a Software Interrupt In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode.
PIC16(L)F720/721 TABLE 15-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/ DONE ADON 79 ANSELB — — ANSB5 ANSB4 — — — — CCP1CON — — DC1 B1 CCP1M3 Name CCP1M2 CCP1M1 CCP1M0 CCPR1L Capture/Compare/PWM Register Low Byte CCPR1H Capture/Compare/PWM Register High Byte 56 107 — — GIE PEIE TMR0IE PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 39 PIR1 TMR1G
PIC16(L)F720/721 15.3 PWM Mode The PWM mode generates a Pulse-Width Modulated signal on the CCP1 pin. The duty cycle, period and resolution are determined by the following registers: • • • • The PWM output (Figure 15-4) has a time base (period) and a time that the output stays high (duty cycle). FIGURE 15-4: PR2 T2CON CCPR1L CCP1CON CCP PWM OUTPUT Period Pulse Width In Pulse-Width Modulation (PWM) mode, the CCP module produces up to a 10-bit resolution PWM output on the CCP1 pin.
PIC16(L)F720/721 15.3.2 PWM PERIOD The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 15-1. EQUATION 15-1: PWM PERIOD PWM Period = PR2 + 1 4 T OSC (TMR2 Prescale Value) Note: TOSC = 1/FOSC When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The CCP1 pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.
PIC16(L)F720/721 15.3.4 PWM RESOLUTION EQUATION 15-4: The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. log 4 PR2 + 1 Resolution = ------------------------------------------ bits log 2 The maximum PWM resolution is 10 bits when PR2 is 255.
PIC16(L)F720/721 TABLE 15-6: Name SUMMARY OF REGISTERS ASSOCIATED WITH PWM Bit 3 Bit 2 Bit 1 Bit 0 Register on Page Bit 7 Bit 6 Bit 5 Bit 4 ANSELB — — ANSB5 ANSB4 — — — — 56 CCP1CON — — DC1 B1 CCP1M3 CCP1M2 CCP1M1 CCP1M0 107 CCPR1L Capture/Compare/PWM Register Low Byte CCPR1H Capture/Compare/PWM Register High Byte — Timer2 module Period Register 105 PR2 T2CON — — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 TMR2 Timer2 module Register 106 105 TRISB TRIS
PIC16(L)F720/721 NOTES: DS40001430E-page 116 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 16.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (AUSART) The AUSART module includes the following capabilities: • • • • • • • • • • The Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution.
PIC16(L)F720/721 FIGURE 16-2: AUSART RECEIVE BLOCK DIAGRAM SPEN CREN RX/DT Baud Rate Generator +1 SPBRG RSR Register MSb Pin Buffer and Control Data Recovery FOSC Multiplier x4 x16 x64 SYNC 1 0 0 BRGH x 1 0 Stop OERR (8) ••• 7 1 LSb 0 START RX9 ÷n n FERR RX9D RCREG Register 8 FIFO Data Bus RCIF RCIE Interrupt The operation of the AUSART module is controlled through two registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) These registers ar
PIC16(L)F720/721 16.1 AUSART Asynchronous Mode The AUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH Mark state which represents a ‘1’ data bit, and a VOL space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission.
PIC16(L)F720/721 16.1.1.4 TSR Status 16.1.1.6 The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: 16.1.1.5 1. 2. 3.
PIC16(L)F720/721 FIGURE 16-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG Word 1 BRG Output (Shift Clock) TX/CK pin Start bit TXIF bit (Transmit Buffer Empty Flag) bit 1 Word 1 bit 7/8 Stop bit Start bit bit 0 Word 2 1 TCY Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg. This timing diagram shows two consecutive transmissions. TABLE 16-1: Name bit 0 1 TCY TRMT bit (Transmit Shift Reg.
PIC16(L)F720/721 16.1.2.2 Receiving Data The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the center of the Start bit and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the Start bit.
PIC16(L)F720/721 16.1.2.7 Address Detection A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems. Address detection is enabled by setting the ADDEN bit of the RCSTA register. Address detection requires 9-bit character reception. When address detection is enabled, only characters with the ninth data bit set will be transferred to the receive FIFO buffer, thereby setting the RCIF interrupt bit of the PIR1 register.
PIC16(L)F720/721 FIGURE 16-5: ASYNCHRONOUS RECEPTION Start bit bit 0 RX/DT pin Start bit bit 7/8 Stop bit bit 1 Rcv Shift Reg Rcv Buffer Reg bit 0 Start bit bit 7/8 Stop bit Word 2 RCREG Word 1 RCREG Read Rcv Buffer Reg RCREG bit 7/8 Stop bit RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.
PIC16(L)F720/721 REGISTER 16-1: R/W-0 CSRC TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 TX9 TXEN(1) SYNC — BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) b
PIC16(L)F720/721 REGISTER 16-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit(1) 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6
PIC16(L)F720/721 16.2 AUSART Baud Rate Generator (BRG) EXAMPLE 16-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, and Asynchronous mode with SYNC = 0 and BRGH = 0 (as seen in Table 16-5): The Baud Rate Generator (BRG) is an 8-bit timer that is dedicated to the support of both the asynchronous and synchronous AUSART operation.
PIC16(L)F720/721 TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0 BAUD RATE FOSC = 16.0000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — 300 0.16 207 1200 1201 0.08 207 1200 0.00 143 1202 0.16 103 1202 0.16 51 2400 2403 0.16 103 2400 0.
PIC16(L)F720/721 TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1 BAUD RATE FOSC = 16.0000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 — — — — — — — — — — — — — — — — — — — 1202 — 0.16 — 207 2400 — — — — 0.00 — 71 2404 0.16 207 2404 0.
PIC16(L)F720/721 16.3 AUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line.
PIC16(L)F720/721 FIGURE 16-6: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TX/CK pin Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ Note: ‘1’ Synchronous Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
PIC16(L)F720/721 16.3.1.4 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the AUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register).
PIC16(L)F720/721 FIGURE 16-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RCREG Note: Timing diagram demonstrates Synchronous Master mode with bit SREN = 1 and bit BRGH = 0.
PIC16(L)F720/721 16.3.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the AUSART for synchronous slave operation: • • • • • SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 1. 2. 3. 4. Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTA register configures the device as a slave.
PIC16(L)F720/721 16.3.2.3 AUSART Synchronous Slave Reception 16.3.2.4 1. The operation of the Synchronous Master and Slave modes is identical (Section 16.3.1.4 “Synchronous Master Reception”), with the following exceptions: 2. • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don’t care” in Slave mode 3. 4. A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep.
PIC16(L)F720/721 16.4 AUSART Operation During Sleep The AUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers. 16.4.
PIC16(L)F720/721 17.0 SSP MODULE OVERVIEW The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripherals or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C™) 17.1 A typical SPI connection between microcontroller devices is shown in Figure 17-1.
PIC16(L)F720/721 FIGURE 17-2: SPI MODE BLOCK DIAGRAM Internal Data Bus Read Write SSPBUF Reg SSPSR Reg SDI bit 0 Shift Clock bit 7 SDO SS Control Enable RA5/SS RA0/SS SSSEL 2 Clock Select Edge Select 2 Edge Select Prescaler 4, 16, 64 SCK TRISx TMR2 Output FOSC 4 SSPM<3:0> DS40001430E-page 138 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 17.1.1 MASTER MODE In Master mode, data transfer can be initiated at any time because the master controls the SCK line. Master mode determines when the slave (Figure 17-1, Processor 2) transmits data via control of the SCK line. 17.1.1.1 Master Mode Operation The SSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF). The SSPSR register shifts the data in and out of the device, MSb first.
PIC16(L)F720/721 FIGURE 17-3: SPI MASTER MODE WAVEFORM Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDO (CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 0 bit 7 Input Sample (SMP = 0) SDI (SMP = 1) bit 0 bit 7 Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF EXAMPLE 17-1: LOOP BANKSEL BTFSS GOTO BANKSEL MOVF MOVWF MOVF MOV
PIC16(L)F720/721 17.1.2 SLAVE MODE For any SPI device acting as a slave, the data is transmitted and received as external clock pulses appear on SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. 17.1.2.1 Slave Mode Operation The SSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first.
PIC16(L)F720/721 FIGURE 17-4: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) bit 6 bit 7 bit 7 bit 5 bit 4 bit 3 bit 2 bit 1 bit
PIC16(L)F720/721 17.1.2.4 Slave Select Operation The SS pin allows Synchronous Slave mode operation. The SPI must be in Slave mode with SS pin control enabled (SSPM<3:0> = 0100). The associated TRIS bit for the SS pin must be set, making SS an input. Note: In Slave Select mode, when: • SS = 0, The device operates as specified in Section 17.1.2 “Slave Mode”. • SS = 1, The SPI module is held in Reset and the SDO pin will be tri-stated.
PIC16(L)F720/721 REGISTER 17-1: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
PIC16(L)F720/721 REGISTER 17-2: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (SPI MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SMP: SPI Data Input Sample Phase bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cl
PIC16(L)F720/721 TABLE 17-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 ANSELC ANSC7 ANSC6 INTCON GIE PEIE PIE1 TMR1GIE ADIE PIR1 TMR1GIF ADIF Bit 5 Bit 2 Bit 1 Bit 0 Register on Page ANSC3 ANSC2 ANSC1 ANSC0 61 RABIE TMR0IF INTF RABIF 38 TXIE SSPIE CCP1IE TMR2IE TMR1IE 39 TXIF SSPIF CCP1IF TMR2IF TMR1IF Bit 4 Bit 3 — — TMR0IE INTE RCIE RCIF PR2 Timer2 module Period Register SSPBUF 40 105 Synchronous Serial Port Receive Buffer/Trans
PIC16(L)F720/721 I2C Mode 17.2 FIGURE 17-8: The SSP module, in I2C mode, implements all slave functions except general call support. It provides interrupts on Start and Stop bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the I2C Standard mode specifications: VDD Data is sampled on the rising edge and shifted out on the falling edge of the clock. This ensures that the SDA signal is valid during the SCL high time.
PIC16(L)F720/721 17.2.2 START AND STOP CONDITIONS During times of no data transfer (Idle time), both the clock line (SCL) and the data line (SDA) are pulled high through external pull-up resistors. The Start and Stop conditions determine the start and stop of data transmission. The Start condition is defined as a high-to-low transition of the SDA line while SCL is high. The Stop condition is defined as a low-to-high transition of the SDA line while SCL is high.
PIC16(L)F720/721 17.2.4 ADDRESSING Once the SSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8 bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock line (SCL). 17.2.4.1 7-bit Addressing In 7-bit Addressing mode (Figure 17-10), the value of register SSPSR<7:1> is compared to the value of register SSPADD<7:1>. The address is compared on the falling edge of the eighth clock (SCL) pulse.
PIC16(L)F720/721 17.2.5 RECEPTION When the R/W bit of the received address byte is clear, the master will write data to the slave. If an address match occurs, the received address is loaded into the SSPBUF register. An address byte overflow will occur if that loaded address is not read from the SSPBUF before the next complete byte is received. An SSP interrupt is generated for each data transfer byte.
2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 17.2.6 TRANSMISSION When the R/W bit of the received address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set and the slave will respond to the master by reading out data. After the address match, an ACK pulse is generated by the slave hardware and the SCL pin is held low (clock is automatically stretched) until the slave is ready to respond. See Section 17.2.7 “Clock Stretching”.
2010-2013 Microchip Technology Inc. CKP UA BF SSPIF 1 SCL S 1 2 1 4 1 5 0 6 7 A9 A8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 3 1 8 9 ACK R/W = 0 1 3 4 5 Cleared in software 2 7 UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address.
PIC16(L)F720/721 17.2.7 CLOCK STRETCHING 2 During any SCL low phase, any device on the I C bus may hold the SCL line low and delay, or pause, the transmission of data. This “stretching” of a transmission allows devices to slow down communication on the bus. The SCL line must be constantly sampled by the master to ensure that all devices on the bus have released SCL for more data. Stretching usually occurs after an ACK bit of a transmission, delaying the first bit of the next byte.
PIC16(L)F720/721 17.2.10 CLOCK SYNCHRONIZATION When the CKP bit is cleared, the SCL output is held low once it is sampled low. Therefore, the CKP bit will not stretch the SCL line until an external I2C master device has already asserted the SCL line low. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have released SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (Figure 17-14). FIGURE 17-14: 17.2.
PIC16(L)F720/721 SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER (I2C MODE) REGISTER 17-3: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be clea
PIC16(L)F720/721 REGISTER 17-4: SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (I2C MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: SPI Data Input Sample Phase bit 1 = Slew Rate Control (limiting) disabled. Operating in I2C Standard mode (100 kHz and 1 MHz).
PIC16(L)F720/721 REGISTER 17-5: SSPMSK: SSP MASK REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPADD to detect I2C address match 0 = The received address bit n is not used to detect I2C addre
PIC16(L)F720/721 18.0 FLASH PROGRAM MEMORY SELF READ/SELF WRITE CONTROL The Flash Program Memory is readable and writable during normal operation of the device. This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers. There are six SFRs used to read/write this memory: • • • • • • PMCON1 PMCON2 PMDATL PMDATH PMADRL PMADRH 18.
PIC16(L)F720/721 FIGURE 18-1: Q1 Flash ADDR FLASH PROGRAM MEMORY READ CYCLE EXECUTION – NORMAL MODE Q2 Q3 Q4 PC Flash DATA Q1 Q2 Q4 Q1 Q2 Q3 Q4 Q1 Q2 PMADRH, PMADRL PC + 1 INSTR (PC) INSTR (PC - 1) Executed here Q3 INSTR (PC + 1) BSF PMCON1, RD Executed here Q3 Q1 Q2 Q3 Q4 PC + 4 PC+3 PMDATH, PMDATL Forced NOP Executed here Q4 INSTR (PC + 3) Forced NOP Executed here Q1 Q2 Q3 Q4 PC + 5 INSTR (PC + 4) INSTR (PC + 3) Executed here INSTR (PC + 4) Executed here RD bit
PIC16(L)F720/721 18.5 Writing to Flash Program Memory A word of the Flash program memory may only be written to if the word is in an unprotected segment of memory. Flash program memory may only be written to if the destination address is in a segment of memory that is not write-protected, as defined in bits WRT<1:0> of the Configuration Word Register 2. Flash program memory must be written in 32-word rows. See Figure 18-2 for more details.
PIC16(L)F720/721 Since data is being written to buffer registers, the writing of the first 31 words of the block appears to occur immediately. The processor will halt internal operations for the typical 2ms, only during the cycle in which the erase takes place (i.e., the last word of the 32-word block erase). This is not Sleep mode as the clocks and peripherals will continue to run.
PIC16(L)F720/721 18.6 Protection Against Spurious Write There are conditions when the device should not write to the program memory. To protect against spurious writes, various mechanisms have been built in. On power-up, WREN is cleared. Also, the Power-up Timer (64 ms duration) prevents program memory writes. The write initiates sequence and the WREN bit helps prevent an accidental write during brown-out, power glitch or software malfunction. REGISTER 18-1: 18.
PIC16(L)F720/721 REGISTER 18-2: PMDATH: PROGRAM MEMORY DATA HIGH REGISTER U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — PMD13 PMD12 PMD11 PMD10 PMD9 PMD8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 PMD<13:8>: The value of the program memory word pointed to by PMADRH and PMADRL after a program memory read command.
PIC16(L)F720/721 REGISTER 18-5: PMADRL: PROGRAM MEMORY ADDRESS LOW REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x PMA7 PMA6 PMA5 PMA4 PMA3 PMA2 PMA1 PMA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 TABLE 18-1: Name PMCON1 PMA<7:0>: Program Memory Read Address bits SUMMARY OF REGISTERS ASSOCIATED WITH PROGRAM MEMORY READ Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
PIC16(L)F720/721 NOTES: DS40001430E-page 166 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 19.0 POWER-DOWN MODE (SLEEP) 19.1 Wake-up from Sleep The Power-down mode is entered by executing a SLEEP instruction. The device can wake-up from Sleep through one of the following events: If the Watchdog Timer is enabled: 1. 2. • • • • • WDT will be cleared but keeps running. PD bit of the STATUS register is cleared. TO bit of the STATUS register is set. Oscillator driver is turned off.
PIC16(L)F720/721 19.2 Wake-up Using Interrupts When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will not be cleared, the TO bit will not be set and the PD bit will not be cleared.
PIC16(L)F720/721 20.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) The device is placed into Program/Verify mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP from 0V to VPP. In Program/Verify mode the program memory, user IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ISCPCLK pin is the clock input.
PIC16(L)F720/721 NOTES: DS40001430E-page 170 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 21.
PIC16(L)F720/721 TABLE 21-2: PIC16(L)F720/721 INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f – f, d f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W wit
PIC16(L)F720/721 21.2 Instruction Descriptions ADDLW Add literal and W Syntax: [ label ] ADDLW Operands: 0 k 255 Operation: (W) + k (W) Status Affected: C, DC, Z Description: The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register. k BCF Bit Clear f Syntax: [ label ] BCF Operands: 0 f 127 0b7 Operation: 0 (f) Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared.
PIC16(L)F720/721 BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT Operands: 0 f 127 0b<7 Operands: None Operation: 00h WDT 0 WDT prescaler, 1 TO 1 PD Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
PIC16(L)F720/721 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
PIC16(L)F720/721 MOVWF Move W to f Syntax: [ label ] MOVF Move f Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 Operation: (W) (f) Operation: (f) (dest) Status Affected: None Status Affected: Z Description: Description: The contents of register f is moved to a destination dependent upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself.
PIC16(L)F720/721 RETFIE Return from Interrupt RETLW Return with literal in W Syntax: [ label ] Syntax: [ label ] Operands: None Operands: 0 k 255 Operation: TOS PC, 1 GIE Operation: k (W); TOS PC Status Affected: None Status Affected: None Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
PIC16(L)F720/721 RLF Rotate Left f through Carry SLEEP Enter Sleep mode Syntax: [ label ] Syntax: [ label ] SLEEP Operands: 0 f 127 d [0,1] Operands: None Operation: Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC16(L)F720/721 SUBWF Subtract W from f XORLW Exclusive OR literal with W Syntax: [ label ] SUBWF f,d Syntax: [ label ] XORLW k Operands: 0 f 127 d [0,1] Operands: 0 k 255 (f) - (W) destination) Operation: Operation: (W) .XOR. k W) Status Affected: C, DC, Z Description: SWAPF Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register.
PIC16(L)F720/721 NOTES: DS40001430E-page 180 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 22.
PIC16(L)F720/721 22.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 22.
PIC16(L)F720/721 22.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC16(L)F720/721 22.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 22.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC16(L)F720/721 23.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias....................................................................................................... -40°C to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS, PIC16F720/721 ........................................................................ -0.
PIC16(L)F720/721 23.1 DC Characteristics: PIC16(L)F720/721-I/E (Industrial, Extended) PIC16LF720/721 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F720/721 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param. No. D001 Sym. VDD Characteristic Min. Typ† Max.
PIC16(L)F720/721 FIGURE 23-1: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR VSS NPOR POR REARM VSS TVLOW(2) Note 1: 2: 3: TPOR(3) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical. 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 23.2 DC Characteristics: PIC16(L)F720/721-I/E (Industrial, Extended) PIC16LF720/721 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F720/721 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param. No. Device Characteristics Conditions Min. Typ† Max. Units — 100 180 A 1.
PIC16(L)F720/721 23.3 DC Characteristics: PIC16(L)F720/721-I/E (Power-Down) PIC16LF720/721 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F720/721 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param. No.
PIC16(L)F720/721 23.4 DC Characteristics: PIC16(L)F720/721-I/E DC CHARACTERISTICS Param. No. Sym. VIL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Min. Typ† Max. Units Conditions Input Low Voltage I/O PORT: D030 — — 0.8 V 4.5V VDD 5.5V — — 0.15 VDD V 1.8V VDD 4.5V with Schmitt Trigger buffer — — 0.2 VDD V 2.0V VDD 5.5V with I2C™ levels — — 0.
PIC16(L)F720/721 23.4 DC Characteristics: PIC16(L)F720/721-I/E (Continued) DC CHARACTERISTICS Param. No. Sym. Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Min. Typ† Max. Units Conditions 2.
PIC16(L)F720/721 23.5 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature-40°C TA +125°C Param. No. Sym. Characteristic TH01 JA Thermal Resistance Junction to Ambient TH02 JC Thermal Resistance Junction to Case TH03 TH04 TH05 TH06 TJMAX PD Maximum Junction Temperature Power Dissipation PINTERNAL Internal Power Dissipation PI/O I/O Power Dissipation Typ. Units 62.2 75.0 89.3 43.0 27.5 23.1 31.1 5.
PIC16(L)F720/721 23.6 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
PIC16(L)F720/721 23.7 AC Characteristics: PIC16F720/721-I/E PIC16F720/721 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C FIGURE 23-3: VDD (V) 5.5 1.8 8 0 16 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. PIC16LF720/721 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C VDD (V) FIGURE 23-4: 3.6 1.8 0 8 16 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
PIC16(L)F720/721 FIGURE 23-5: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 ± 5% Temperature (°C) 85 ± 3% 60 ± 2% 25 0 ± 5% -40 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 FIGURE 23-6: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 CLKIN OS02 OS03 CLKOUT TABLE 23-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param. No. Sym. Characteristic Min. Typ† Max.
PIC16(L)F720/721 TABLE 23-2: OSCILLATOR PARAMETERS(1) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. No. OS08 OS08 OS10* Sym HFOSC MFOSC Characteristic Internal Calibrated HFINTOSC Frequency(2, 3) Internal Calibrated MFINTOSC Frequency(2, 3) TIOSC ST HFINTOSC 16 MHz and MFINTOSC 500 kHz Oscillator Wake-up from Sleep Start-up Time Freq. Tolerance Min. 2% — 16.0 — MHz 0°C TA +60°C, VDD 2.5V 3% — 16.
PIC16(L)F720/721 FIGURE 23-7: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 23-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. No. OS11* OS12* OS13* Sym. TOSH2CKL Characteristic Min. Typ† Max.
PIC16(L)F720/721 FIGURE 23-8: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR + VHYST VBOR (Device not in Brown-out Reset) (Device in Brown-out Reset) TBORDC Reset (due to BOR) TPWRT(1) Note 1: The additional delay of TPWRT, prior to releasing Reset, only occurs when the Power-up Timer is enabled (PWRTE = 0). 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 TABLE 23-4: RESET, WATCHDOG TIME, POWER-UP TIMER, AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. No. Sym. Characteristic Min. Typ† Max. Units Conditions 30* TMCL MCLR Pulse Width (low) 2 5 — — — — s s VDD = 5V, -40°C to +85°C VDD = 5V(1) 31 TWDT Standard Watchdog Timer Time-out Period (No Prescaler)(2) 10 10 18 18 27 33 ms ms VDD = 3.3V-5V, -40°C to +85°C VDD = 3.
PIC16(L)F720/721 TABLE 23-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. No. Sym. TT0H 40* 41* TT0L Characteristic Min. Typ† Max. Units No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns Greater of: 20 or TCY + 40 N — — ns Synchronous, No Prescaler 0.
PIC16(L)F720/721 TABLE 23-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. No. Sym. CC01* TccL Characteristic CCP Input Low Time CC02* TccH CCP Input High Time CC03* TccP CCP Input Period Min. Max. Units No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns No Prescaler 0.
PIC16(L)F720/721 TABLE 23-8: PIC16F720/721 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param. No. Sym. Characteristic AD130* TAD A/D Clock Period A/D Internal RC Oscillator Period AD131 TCNV Min. Typ† Max. Units 1.0 — 9.0 S VDD 2.0V(2) 4.0 — 16.0 S VDD 2.0V(2) 1.0 2.0 6.0 S — 10.5 — TAD Set GO/DONE bit to new data in A/D Result register 2 — S VDD = 3.
PIC16(L)F720/721 FIGURE 23-12: PIC16F720/721 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO (TOSC/2 + TCY(1)) AD134 1 TCY AD131 Q4 AD130 A/D CLK 7 A/D Data 6 5 4 3 2 1 0 NEW_DATA OLD_DATA ADRES ADIF 1 TCY GO DONE Sampling Stopped AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
PIC16(L)F720/721 FIGURE 23-14: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING CK US125 DT US126 Note: Refer to Figure 23-2 for load conditions. TABLE 23-10: USART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. No. Symbol Characteristic Min. Max.
PIC16(L)F720/721 FIGURE 23-16: SPI MASTER MODE TIMING (CKE = 1, SMP = 1) SS SP81 SCK (CKP = 0) SP71 SP72 SP79 SP73 SCK (CKP = 1) SP80 LSb bit 6 - - - - - -1 MSb SDO SP78 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note 1: Refer to Figure 23-2 for load conditions.
PIC16(L)F720/721 FIGURE 23-18: SS SPI SLAVE MODE TIMING (CKE = 1) SP82 SP70 SP83 SCK (CKP = 0) SP71 SP72 SCK (CKP = 1) SP80 SDO MSb bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note 1: Refer to Figure 23-2 for load conditions. 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 TABLE 23-11: SPI MODE REQUIREMENTS Param. No. SP70* Symbol Characteristic TSSL2SCH, TSSL2SCL SS to SCK or SCK input Min. Typ† Max.
PIC16(L)F720/721 FIGURE 23-19: I2C™ BUS START/STOP BITS TIMING SCL SP93 SP91 SP90 SP92 SDA Stop Condition Start Condition Note 1: Refer to Figure 23-2 for load conditions. TABLE 23-12: I2C™ BUS START/STOP BITS REQUIREMENTS Param. No. Symbol SP90* TSU:STA SP91* THD:STA SP92* TSU:STO Characteristic Max.
PIC16(L)F720/721 TABLE 23-13: I2C™ BUS DATA REQUIREMENTS Param. No. 100* Symbol THIGH Characteristic Clock high time Min. Max. Units Conditions 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1.5TCY — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.
PIC16(L)F720/721 24.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS FIGURE 24-1: PIC16F720/721 MAX IDD vs. FOSC OVER VDD, EC MODE 1800 5.0V 3.6V Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) +3ı (-40°C to 125°C) 1600 3.0V 1400 IDD (µA) 1200 2.5V 1000 800 1.8V 600 400 200 0 0 2 4 6 8 10 12 14 16 18 FOSC (MHz) FIGURE 24-2: PIC16F720/721 TYPICAL IDD vs.
PIC16(L)F720/721 FIGURE 24-3: PIC16LF720/721 MAX. IDD vs. FOSC OVER VDD, EC MODE 2000 1800 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) +3ı (-40°C to 125°C) 1600 3.6V 3.3V 3.0V IDD (µA) 1400 1200 2.5V 1000 2.0V 800 1.8V 600 400 200 0 0 2 4 6 8 10 12 14 16 18 FOSC (MHz) PIC16LF720/721 TYPICAL IDD vs. FOSC OVER VDD, EC MODE FIGURE 24-4: 1800 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) +3ı (-40°C to 125°C) 1600 3.6V 3.3V 1400 3.
PIC16(L)F720/721 FIGURE 24-5: PIC16F720/721 MAX. IDD vs. FOSC OVER VDD, MFINTOSC 350 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) +3 (-40°C to 125°C) 300 5V 250 3V 2.5V IDD (µA) 200 1.8V 150 100 50 0 0 100 200 300 400 500 600 FOSC (kHZ) FIGURE 24-6: PIC16F720/721 TYPICAL IDD vs. FOSC OVER VDD, MFINTOSC 350 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) +3 (-40°C to 125°C) 300 250 IDD (µA) 200 5V 150 3V 2.5V 1.
PIC16(L)F720/721 FIGURE 24-7: PIC16LF720/721 MAX. IDD vs. FOSC OVER VDD, MFINTOSC 250 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) +3 (-40°C to 125°C) 200 3.6V 3V 2.5V 150 IDD (µA) 1.8V 100 50 0 0 100 200 300 400 500 600 FOSC (kHZ) FIGURE 24-8: PIC16LF720/721 TYPICAL IDD vs. FOSC OVER VDD, MFINTOSC 250 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) +3 (-40°C to 125°C) 200 IDD (µA) 150 3.6V 3V 2.5V 1.
PIC16(L)F720/721 FIGURE 24-9: PIC16F720/721 MAX. IDD vs. FOSC OVER VDD, HFINTOSC 2000 5.0V 1800 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) +3ı (-40°C to 125°C) 1600 3.6V 2.5V IDD (µA) 1400 1200 1.8V 1000 800 600 400 200 0 0 2 4 6 8 10 12 14 16 18 FOSC (MHz) FIGURE 24-10: PIC16F720/721 TYPICAL IDD vs. FOSC OVER VDD, HFINTOSC 2000 1800 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) +3ı (-40°C to 125°C) 1600 5.0V 3.6V 1400 IDD (µA) 2.
PIC16(L)F720/721 FIGURE 24-11: PIC16LF720/721 MAX. IDD vs. FOSC OVER VDD, HFINTOSC 2500 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) +3ı (-40°C to 125°C) 2000 3.6V IDD (µA) 3.0V 1500 2.5V 1.8V 1000 500 0 0 2 4 6 8 10 12 14 16 18 FOSC (MHz) FIGURE 24-12: PIC16LF720/721 TYPICAL IDD vs. FOSC OVER VDD, HFINTOSC 2000 3.6V Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) +3ı (-40°C to 125°C) 1800 1600 3.0V 1400 IDD (µA) 2.5V 1200 1000 1.
PIC16(L)F720/721 FIGURE 24-13: PIC16F720/721 BASE IPD vs. VDD 80 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) +3 (-40°C to 125°C) 70 Max.125°C 60 IPD (µA) 50 Max. 85°C 40 30 Typ. 25°C 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 VDD (V) 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 FIGURE 24-14: PIC16LF720/721 MAXIMUM BASE IPD vs. VDD 8 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) +3 (-40°C to 125°C) 7 6 Max. 125°C IPD (µA) 5 4 3 Max. 85°C 2 1 0 1.5 2 2.5 3 3.5 4 VDD (V) FIGURE 24-15: PIC16LF720/721 TYPICAL BASE IPD vs. VDD 250 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) +3 (-40°C to 125°C) 200 Typ. IPD (nA) 150 100 50 0 1.5 2 2.5 3 3.
PIC16(L)F720/721 FIGURE 24-16: PIC16F720/721 WDT IPD vs. VDD 80 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) +3 (-40°C to 125°C) 70 Max. 125°C 60 IPD (µA) 50 Max. 85°C 40 30 Typ. 25°C 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 VDD (V) FIGURE 24-17: PIC16LF720/721 WDT IPD vs. VDD 14 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) +3 (-40°C to 125°C) 12 10 Max. 125°C IPD (µA) 8 6 Max. 85°C 4 2 Typ. 25°C 0 1.5 2 2.5 3 3.
PIC16(L)F720/721 FIGURE 24-18: PIC16F720/721 FIXED VOLTAGE REFERENCE IPD vs. VDD 300 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) +3 (-40°C to 125°C) 250 200 IPD (µA) Max. 125°C 150 Max. 85°C 100 Typ. 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 VDD (V) FIGURE 24-19: PIC16LF720/721 FIXED VOLTAGE REFERENCE IPD vs. VDD 40 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) +3 (-40°C to 125°C) 35 Max. 125°C 30 25 IPD (µA) Max. 85°C 20 Typ. 15 10 5 0 1.
PIC16(L)F720/721 FIGURE 24-20: PIC16F720/721 BOR IPD vs. VDD 80 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) +3 (-40°C to 125°C) 70 60 Max. 125°C IPD (µA) 50 Max. 85°C 40 30 Typ. 25°C 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 VDD (V) FIGURE 24-21: PIC16LF720/721 BOR IPD vs. VDD 30 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) +3 (-40°C to 125°C) 25 Max. 125°C IPD (µA) 20 15 Max. 85°C 10 Typ. 25°C 5 0 1.5 2 2.5 3 3.
PIC16(L)F720/721 FIGURE 24-22: TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE 1.8 1.6 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 1.4 Max. -40° VIN (V) 1.2 Typ. 25° 1 Min. 125° 0.8 0.6 0.4 1.8 3.6 5.5 VDD (V) FIGURE 24-23: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE 3.5 3.0 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) VIH Max. -40°C 2.5 VIN (V) 2.0 1.5 VIH Min. 125°C 1.
PIC16(L)F720/721 FIGURE 24-24: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE 3.0 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 2.5 VIL Max. -40°C VIN (V) 2.0 1.5 1.0 VIL Min. 125°C 0.5 0.0 1.8 3.6 5.5 VDD (V) FIGURE 24-25: VOH vs. IOH OVER TEMPERATURE, VDD = 5.5V 5.6 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 5.5 VOH (V) 5.4 5.3 Max. -40° Typ. 25° 5.2 Min. 125° 5.1 5 -0.
PIC16(L)F720/721 FIGURE 24-26: VOH vs. IOH OVER TEMPERATURE, VDD = 3.6V 3.8 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 3.6 3.4 VOH (V) Max. -40° 3.2 Typ. 25° 3 Min. 125° 2.8 2.6 -0.2 -1.0 -1.8 -2.6 -3.4 -4.2 -5.0 IOH (mA) VOH vs. IOH OVER TEMPERATURE, VDD = 1.8V FIGURE 24-27: 2 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 1.8 1.6 Max. -40° 1.4 VOH (V) 1.2 Typ. 25° 1 0.8 0.6 Min. 125° 0.
PIC16(L)F720/721 FIGURE 24-28: VOL vs. IOL OVER TEMPERATURE, VDD = 5.5V 0.5 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 0.45 0.4 0.35 Max. 125° VOL (V) 0.3 0.25 0.2 Typ. 25° 0.15 0.1 Min. -40° 0.05 0 5.0 6.0 7.0 8.0 9.0 10.0 IOL (mA) FIGURE 24-29: VOL vs. IOL OVER TEMPERATURE, VDD = 3.6 0.9 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 0.8 0.7 0.6 Max. 125° VOL (V) 0.5 0.4 Typ. 25° 0.3 0.
PIC16(L)F720/721 FIGURE 24-30: VOL vs. IOL OVER TEMPERATURE, VDD = 1.8V 1.2 1 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 0.8 VOL (V) Max. 125° 0.6 0.4 0.2 Min. -40° 0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 IOL (mA) FIGURE 24-31: PIC16F720/721 PWRT PERIOD 105 95 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. -40°C TIME (ms) 85 75 Typ. 25°C 65 Min. 125°C 55 45 1.8V 2V 2.2V 2.4V 3V 3.
PIC16(L)F720/721 FIGURE 24-32: PIC16F720/721 WDT TIME-OUT PERIOD 24.00 22.00 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. -40°C 20.00 TIME (ms) 18.00 Typ. 25°C 16.00 14.00 Min. 125°C 12.00 10.00 1.8V 2V 2.2V 2.4V 3V 3.6V 4V 4.5V 5V VDD FIGURE 24-33: PIC16F720/721 HFINTOSC WAKE-UP FROM SLEEP START-UP TIME 6.0 5.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 5.0 4.5 Max. TIME (us) 4.0 3.5 3.0 Typ.
PIC16(L)F720/721 FIGURE 24-34: PIC16F720/721 A/D INTERNAL RC OSCILLATOR PERIOD 6.0 5.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Period (µs) 4.0 3.0 Max. Min. 2.0 1.0 0.0 1.8V 3.6V 5.5V VDD(V) FIGURE 24-35: TYPICAL FVR (X1 AND X2) VS. SUPPLY VOLTAGE (V) NORMALIZED AT 3.0V 1.5 Percent Change (%) 1 0.5 0 -0.5 -1 -1.5 1.8 2.5 3 3.6 4.2 5.5 Voltage DS40001430E-page 228 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 FIGURE 24-36: TYPICAL FVR CHANGE VS. TEMPERATURE NORMALIZED AT 25°C 1.5 1 Percent Change (%) 0.5 0 -0.5 -1 -1.5 -2 -2.5 -3 -40 0 45 85 125 Temperature (°C) 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 NOTES: DS40001430E-page 230 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 25.0 PACKAGING INFORMATION 25.1 Package Marking Information Example 20-Lead PDIP (300 mil) XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN PIC16F721-E/P e3 0810017 20-Lead QFN (4x4x0.9 mm) PIN 1 Example PIN 1 PIC16 F721 E/ML 810017 e3 Legend: XX...
PIC16(L)F720/721 25.1 Package Marking Information 20-Lead SOIC (7.50 mm) Example PIC16F720 -I/SO e3 0810017 20-Lead SSOP (5.30 mm) Example PIC16F720 -I/SS e3 0810017 Legend: XX...X Y YY WW NNN e3 * Note: * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free.
PIC16(L)F720/721 25.2 Package Details The following sections give the technical details of the packages.
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PIC16(L)F720/721 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001430E-page 236 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001430E-page 238 2010-2013 Microchip Technology Inc.
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PIC16(L)F720/721 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001430E-page 240 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (September 2010) Original release of this document. Revision B (March 2011) Updated the Electrical Specifications section. APPENDIX B: MIGRATING FROM OTHER PIC® DEVICES This shows a comparison of features in the migration from another PIC® device, the PIC16F720, to the PIC16F721 device. B.
PIC16(L)F720/721 NOTES: DS40001430E-page 242 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 INDEX A B A/D BF bit ........................................................................ 145, 157 Block Diagrams (CCP) Capture Mode Operation ............................... 108 ADC ............................................................................ 75 ADC Transfer Function............................................... 82 Analog Input Model..................................................... 82 AUSART Receive .....................................................
PIC16(L)F720/721 CCP. See Capture/Compare/PWM (CCP) CCP1CON Register ............................................................ 16 CCPR1H Register ............................................................... 16 CCPR1L Register................................................................ 16 CCPxCON Register .......................................................... 107 CKE bit ...................................................................... 145, 157 CKP bit .....................................
PIC16(L)F720/721 MPLAB REAL ICE In-Circuit Emulator System................. 183 MPLINK Object Linker/MPLIB Object Librarian ................ 182 O OPCODE Field Descriptions ............................................. 171 OPTION_REG Register ...................................................... 91 OSCCON Register .............................................................. 67 Oscillator Associated registers............................................ 69, 104 Oscillator Module EC .......................
PIC16(L)F720/721 TRISA (Tri-State PORTA) ........................................... 46 TRISB (Tri-State PORTB) ........................................... 55 TRISC (Tri-State PORTC) .......................................... 61 TXSTA (Transmit Status and Control) ...................... 125 WPUB (Weak Pull-up PORTB) ................................... 55 Reset................................................................................... 25 Resets Associated Registers ...................................
PIC16(L)F720/721 TRISA Register ............................................................. 17, 46 TRISB ................................................................................. 54 TRISB Register ............................................................. 17, 55 TRISC ................................................................................. 60 TRISC Register ............................................................. 17, 61 TXREG........................................................
PIC16(L)F720/721 NOTES: DS40001430E-page 248 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC16(L)F720/721 NOTES: DS40001430E-page 250 2010-2013 Microchip Technology Inc.
PIC16(L)F720/721 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. X(1) PART NO.
PIC16(L)F720/721 NOTES: DS40001430E-page 252 2010-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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