Datasheet

© 2007 Microchip Technology Inc. DS39597C-page 95
PIC16F72
FIGURE 14-5: CLKO AND I/O TIMING
TABLE 14-2: CLKO AND I/O TIMING REQUIREMENTS
Note: Refer to Figure 14-3 for load conditions.
OSC1
CLKO
I/O Pin
(Input)
I/O Pin
(Output)
Q4
Q1
Q2 Q3
10
13
14
17
20, 21
19
18
15
11
12
16
Old Value
New Value
Param
No.
Symbol Characteristic Min Typ† Max Units Conditions
10* TosH2ckL OSC1↑ to CLKO↓ — 75 200 ns (Note 1)
11* TosH2ckH OSC1↑ to CLKO↑ — 75 200 ns (Note 1)
12* TckR CLKO rise time — 35 100 ns (Note 1)
13* TckF CLKO fall time — 35 100 ns (Note 1)
14* TckL2ioV CLKO↓ to Port out valid — — 0.5 T
CY + 20 ns (Note 1)
15* TioV2ckH Port in valid before CLKO↑ T
OSC + 200 — — ns (Note 1)
16* TckH2ioI Port in hold after CLKO↑ 0——ns(Note 1)
17* TosH2ioV OSC1↑ (Q1 cycle) to Port out valid — 100 255 ns
18* TosH2ioI OSC1↑ (Q2 cycle) to
Port input invalid (I/O in
hold time)
Standard (F) 100 — — ns
Extended (LF) 200 — — ns
19* TioV2osH Port input valid to OSC1↑ (I/O in setup time) 0 — — ns
20* TioR Port output rise time Standard (F) — 10 40 ns
Extended (LF) — — 145 ns
21* TioF Port output fall time Standard (F) — 10 40 ns
Extended (LF) — — 145 ns
22††* T
INP INT pin high or low time TCY ——ns
23††* T
RBP RB7:RB4 change INT high or low time TCY ——ns
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
†† These parameters are asynchronous events, not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x T
OSC.