Datasheet

PIC16F72
DS39597C-page 72 © 2007 Microchip Technology Inc.
FIGURE 11-12: WAKE-UP FROM SLEEP THROUGH INTERRUPT
11.15 Program Verification/
Code Protection
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
11.16 ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations, where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are read-
able and writable during program/verify. It is recom-
mended that only the four Least Significant bits of the
ID location are used.
11.17 In-Circuit Serial Programming
PIC16F72 microcontrollers can be serially programmed
while in the end application circuit. This is simply done
with two lines for clock and data and three other lines for
power, ground, and the programming voltage (see
Figure 11-13 for an example). This allows customers to
manufacture boards with unprogrammed devices, and
then program the microcontroller just before shipping
the product. This also allows the most recent firmware
or a custom firmware to be programmed.
For general information of serial programming, please
refer to the In-Circuit Serial Programming™ (ICSP™)
Guide (DS30277). For specific details on programming
commands and operations for the PIC16F72 devices,
please refer to the latest version of the PIC16F72
FLASH Program Memory Programming Specification
(DS39588).
FIGURE 11-13: TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKO
(4)
INT pin
INTF Flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
PC PC+1 PC+2
Inst(PC) = SLEEP
Inst(PC - 1)
Inst(PC + 1)
SLEEP
Processor in
SLEEP
Interrupt Latency
(Note 2)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h)
Inst(0005h)
Inst(0004h)
Dummy cycle
PC + 2 0004h 0005h
Dummy cycle
T
OST
(2)
PC+2
Note 1: XT, HS or LP Oscillator mode assumed.
2: T
OST = 1024 TOSC (drawing not to scale) This delay will not be there for RC Osc mode.
3: GIE = ‘1' assumed. In this case, after wake-up, the processor jumps to the interrupt routine.
If GIE = ‘0', execution will continue in-line.
4: CLKO is not available in these Osc modes, but shown here for timing reference.
External
Connector
Signals
To Normal
Connections
To Normal
Connections
PIC16F72
V
DD
VSS
MCLR/VPP
RB6
RB7
+5V
0V
V
PP
CLK
Data I/O
VDD
* * *
*
*
Isolation devices (as required).