Datasheet

PIC16F72
DS39597C-page 70 © 2007 Microchip Technology Inc.
11.13 Watchdog Timer (WDT)
The Watchdog Timer is a free running, on-chip RC
oscillator that does not require any external compo-
nents. This RC oscillator is separate from the RC oscil-
lator of the OSC1/CLKI pin. That means that the WDT
will run, even if the clock on the OSC1/CLKI and OSC2/
CLKO pins of the device has been stopped, for
example, by execution of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watchdog
Timer Wake-up). The TO
bit in the STATUS register will
be cleared upon a Watchdog Timer time-out.
The WDT can be permanently disabled by clearing
configuration bit WDTEN (see Section 11.1).
WDT time-out period values may be found in the Elec-
trical Specifications section under parameter #31. Val-
ues for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler) may be assigned
using the OPTION register.
FIGURE 11-11: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 11-7: SUMMARY OF WATCHDOG TIMER REGISTERS
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and the postscaler, if
assigned to the WDT, and prevent it from
timing out and generating a device
RESET condition.
2: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but
the prescaler assignment is not changed.
From TMR0 Clock Source
(Figure 4-1)
To TMR0 (Figure 4-1)
Postscaler
WDT Timer
WDT
Enable Bit
0
1
M
U
X
PSA
8 - to - 1 MUX
PS2:PS0
0
1
MUX
PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION register.
8
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2007h Config. bits (1) BOREN
(1)
— CP PWRTEN
(1)
WDTEN FOSC1 FOSC0
81h,181h OPTION
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 11-1 for operation of these bits.