Datasheet

© 2007 Microchip Technology Inc. DS39597C-page 55
PIC16F72
FIGURE 10-1: A/D BLOCK DIAGRAM
FIGURE 10-2: ANALOG INPUT MODEL
(Input Voltage)
V
AIN
VREF
(Reference
Voltage)
V
DD
PCFG2:PCFG0
CHS2:CHS0
000 or
010 or
100
001 or
011 or
101
RA5/AN4
RA3/AN3/V
REF
RA2/AN2
RA1/AN1
RA0/AN0
100
011
010
001
000
A/D
Converter
CPIN
VA
Rs
ANx
5 pF
V
DD
VT = 0.6 V
V
T = 0.6 V
I leakage
R
IC ≤ 1 k
Sampling
Switch
SS
R
SS
CHOLD
= DAC capacitance
V
SS
6V
Sampling Switch
5V
4V
3V
2V
567891011
( kΩ )
VDD
= 51.2 pF
± 500 nA
Legend:
C
PIN
VT
I leakage
R
IC
SS
C
HOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions