Datasheet

PIC16F72
DS39597C-page 30 © 2007 Microchip Technology Inc.
5.2 Timer1 Operation in Timer Mode
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is F
OSC/4. The synchronize control bit T1SYNC
(T1CON<2>) has no effect, since the internal clock is
always in sync.
5.3 Timer1 Counter Operation
Timer1 may operate in Asynchronous or Synchronous
mode, depending on the setting of the TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a rising edge. After Timer1
is enabled in Counter mode, the module must first have
a falling edge before the counter begins to increment.
5.4 Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI when bit T1OSCEN is
set, or on pin RC0/T1OSO/T1CKI when bit T1OSCEN
is cleared.
If T1SYNC
is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The
prescaler stage is an asynchronous ripple counter.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut-off. The
prescaler, however, will continue to increment.
FIGURE 5-1: TIMER1 INCREMENTING EDGE
FIGURE 5-2: TIMER1 BLOCK DIAGRAM
T1CKI
(Default High)
T1CKI
(Default Low)
Note: Arrows indicate counter increments.
TMR1H
TMR1L
T1OSC
T1SYNC
TMR1CS
T1CKPS1:T1CKPS0
Q Clock
T1OSCEN
Enable
Oscillator
(1)
FOSC/4
Internal
Clock
TMR1ON
On/Off
Prescaler
1, 2, 4, 8
Synchronize
det
1
0
0
1
Synchronized
Clock Input
2
RC0/T1OSO/T1CKI
RC1/T1OSI
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
Set Flag bit
TMR1IF on
Overflow
TMR1
(2)