Datasheet
© 2007 Microchip Technology Inc. DS39597C-page 9
PIC16F72
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details on
page:
Bank 0
00h
(1)
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 19
01h TMR0 Timer0 Module’s Register xxxx xxxx 27,13
02h
(1)
PCL Program Counter's (PC) Least Significant Byte 0000 0000 18
03h
(1)
STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 12
04h
(1)
FSR Indirect Data Memory Address Pointer xxxx xxxx 19
05h PORTA
— — PORTA Data Latch when written: PORTA pins when read --0x 0000 21
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx 23
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx 25
08h — Unimplemented — —
09h — Unimplemented — —
0Ah
(1,2)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 18
0Bh
(1)
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 14
0Ch PIR1
—ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 16
0Dh — Unimplemented — —
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 29
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 29
10h T1CON
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 29
11h TMR2 Timer2 Module’s Register 0000 0000 33
12h T2CON
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 34
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 43,48
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 45
15h CCPR1L Capture/Compare/PWM Register (LSB) xxxx xxxx 38,39,41
16h CCPR1H Capture/Compare/PWM Register (MSB) xxxx xxxx 38,39,41
17h CCP1CON
— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 37
18h-1Dh — Unimplemented — —
1Eh ADRES A/D Result Register xxxx xxxx 53
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE
—ADON0000 00-0 53
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from any bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
3: This bit always reads as a ‘1’.