PIC16F72 Data Sheet 28-Pin, 8-Bit CMOS FLASH Microcontoller with A/D Converter © 2007 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC16F72 28-Pin, 8-Bit CMOS FLASH MCU with A/D Converter • PIC16F72 High Performance RISC CPU: PDIP, SOIC, SSOP •1 2 3 4 5 6 7 8 9 10 11 12 13 14 MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS VSS OSC1/CLKI OSC2/CLKO RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL QFN Peripheral Features: CMOS Technology: • • • • • Low power, high speed CMOS FLASH technology Fully static design Wide operating voltage range: 2.0V to 5.5V Industrial temperature range Low power consumption: - < 0.
PIC16F72 Key Reference Manual Features PIC16F72 Operating Frequency RESETS and (Delays) FLASH Program Memory - (14-bit words, 1000 E/W cycles) Data Memory - RAM (8-bit bytes) Interrupts I/O Ports Timers Capture/Compare/PWM Modules Serial Communications 8-bit A/D Converter Instruction Set (No. of Instructions) DC - 20 MHz POR, BOR, (PWRT, OST) 2K 128 8 PORTA, PORTB, PORTC Timer0, Timer1, Timer2 1 SSP 5 channels 35 DS39597C-page 2 © 2007 Microchip Technology Inc.
PIC16F72 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Memory Organization ................................................................................................................................................................... 7 3.0 I/O Ports ........................................................................................
PIC16F72 NOTES: DS39597C-page 4 © 2007 Microchip Technology Inc.
PIC16F72 1.0 DEVICE OVERVIEW The program memory contains 2K words, which translate to 2048 instructions, since each 14-bit program memory word is the same width as each device instruction. The data memory (RAM) contains 128 bytes. This document contains device specific information for the operation of the PIC16F72 device. Additional information may be found in the PIC™ Mid-Range MCU Reference Manual (DS33023), which may be downloaded from the Microchip website.
PIC16F72 TABLE 1-1: PIC16F72 PINOUT DESCRIPTION PDIP, SOIC, SSOP Pin# MLF Pin# I/O/P Type OSC1/CLKI 9 6 I OSC2/CLKO 10 7 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, the OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 26 I/P ST Master Clear (Reset) input or programming voltage input. This pin is an active low RESET to the device.
PIC16F72 2.0 MEMORY ORGANIZATION There are two memory blocks in the PIC16F72 device. These are the program memory and the data memory. Each block has separate buses so that concurrent access can occur. Program memory and data memory are explained in this section. Program memory can be read internally by the user code (see Section 7.0). The data memory can further be broken down into the general purpose RAM and the Special Function Registers (SFRs).
PIC16F72 FIGURE 2-2: PIC16F72 REGISTER FILE MAP File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON ADRES ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h General Purpose Register File Address Indirect addr.
PIC16F72 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in the peripheral feature section. The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device.
PIC16F72 TABLE 2-1: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details on POR, BOR page: Bank 1 80h(1) INDF 81h OPTION 82h(1) PCL 83h(1) STATUS 84h(1) FSR Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 RBPU INTEDG T0CS T0SE PS2 PS1 PS0 1111 1111 0000 0000 18 PD Z DC C 0001 1xxx 12 xxxx xxxx 19 Program Counter's (PC) Least Significant Byte IR
PIC16F72 TABLE 2-1: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details on POR, BOR page: Bank 2 100h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 101h TMR0 Timer0 Module’s Register xxxx xxxx 27 102h(1 PCL Program Counter's (PC) Least Significant Byte 0000 0000 18 103h(1) STATUS 0001 1xxx 12 104h(1) FSR xxxx xxxx 19 105h — 106h IRP RP
PIC16F72 2.2.2.1 STATUS Register The STATUS register, shown in Register 2-1, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
PIC16F72 2.2.2.2 OPTION Register Note: The OPTION register is a readable and writable register that contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0, and the weak pull-ups on PORTB. REGISTER 2-2: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer.
PIC16F72 2.2.2.3 INTCON Register Note: The INTCON Register is a readable and writable register that contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts. REGISTER 2-3: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16F72 2.2.2.4 PIE1 Register This register contains the individual enable bits for the peripheral interrupts. Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.
PIC16F72 2.2.2.5 PIR1 Register This register contains the individual flag bits for the Peripheral interrupts.
PIC16F72 2.2.2.6 Note: PCON Register Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent RESETS to see if BOR is clear, indicating a brown-out has occurred.
PIC16F72 2.3 PCL and PCLATH Figure 2-3 shows the four situations for the loading of the PC. The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 13-bits wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called the PCH register. This register contains the PC<12:8> bits and is not directly readable or writable. All updates to the PCH register go through the PCLATH register.
PIC16F72 2.3.1 COMPUTED GOTO 2.4 A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note, “Implementing a Table Read" (AN556). 2.3.2 STACK The stack allows a combination of up to eight program calls and interrupts to occur.
PIC16F72 FIGURE 2-5: DIRECT/INDIRECT ADDRESSING Direct Addressing RP1:RP0 6 Indirect Addressing From Opcode 0 IRP 7 Bank Select Bank Select Location Select 00 01 10 FSR Register 0 Location Select 11 00h 80h 100h 180h 7Fh FFh 17Fh 1FFh Data Memory(1) Bank 0 Bank 1 Bank 2 Bank 3 Note 1: For register file map detail, see Figure 2-2. DS39597C-page 20 © 2007 Microchip Technology Inc.
PIC16F72 3.0 I/O PORTS FIGURE 3-1: Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the PIC™ Mid-Range MCU Reference Manual, (DS33023). 3.1 Data Bus D Q VDD WR Port VDD Q CK P Data Latch PORTA and the TRISA Register PORTA is a 6-bit wide, bi-directional port.
PIC16F72 TABLE 3-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 bit 0 TTL Input/output or analog input. RA1/AN1 bit 1 TTL Input/output or analog input. RA2/AN2 bit 2 TTL Input/output or analog input. RA3/AN3/VREF bit 3 TTL Input/output or analog input or VREF. RA4/T0CKI bit 4 ST Input/output or external clock input for Timer0. Output is open drain type. RA5/AN4/SS bit 5 TTL Input/output or analog input or slave select input for synchronous serial port.
PIC16F72 3.2 PORTB and the TRISB Register PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin).
PIC16F72 TABLE 3-3: PORTB FUNCTIONS Name Bit# Buffer Function RB0/INT bit 0 TTL/ST(1) RB1 bit 1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit 2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit 3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit 4 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. RB5 bit 5 TTL Input/output pin (with interrupt-on-change).
PIC16F72 3.3 PORTC and the TRISC Register PORTC is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). PORTC is multiplexed with several peripheral functions (Table 3-5).
PIC16F72 TABLE 3-5: PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit 0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input. RC1/T1OSI bit 1 ST Input/output port pin or Timer1 oscillator input. RC2/CCP1 bit 2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1 output. RC3/SCK/SCL bit 3 ST RC3 can also be the synchronous serial clock for both SPI and I2C modes.
PIC16F72 4.0 TIMER0 MODULE Counter mode is selected by setting bit T0CS (OPTION<5>). In Counter mode, Timer0 will increment, either on every rising or falling edge of pin RA4/ T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 4.3.
PIC16F72 4.3 Using Timer0 with an External Clock Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa. This prescaler is not readable or writable (see Figure 4-1). When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI, with the internal phase clocks, is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks.
PIC16F72 5.0 TIMER1 MODULE 5.
PIC16F72 5.2 Timer1 Operation in Timer Mode 5.4 Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is FOSC/4. The synchronize control bit T1SYNC (T1CON<2>) has no effect, since the internal clock is always in sync. 5.3 Counter mode is selected by setting bit TMR1CS. In this mode, the timer increments on every rising edge of clock input on pin RC1/T1OSI when bit T1OSCEN is set, or on pin RC0/T1OSO/T1CKI when bit T1OSCEN is cleared.
PIC16F72 5.5 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt on overflow, that will wake-up the processor. However, special precautions in software are needed to read/write the timer (Section 5.5.1).
PIC16F72 5.9 Resetting Timer1 Register Pair (TMR1H, TMR1L) 5.10 Timer1 Prescaler The prescaler counter is cleared on writes to the TMR1H or TMR1L registers. TMR1H and TMR1L registers are not reset to 00h on a POR, or any other RESET, except by the CCP1 special event triggers. T1CON register is reset to 00h on a Power-on Reset or a Brown-out Reset, which shuts off the timer and leaves a 1:1 prescale. In all other RESETS, the register is unaffected.
PIC16F72 6.0 TIMER2 MODULE The Timer2 module timer has the following features: • • • • • • • 8-bit timer (TMR2 register) 8-bit period register (PR2) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR2 match of PR2 SSP module optional use of TMR2 output to generate clock shift Timer2 has a control register, shown in Register 6-1.
PIC16F72 REGISTER 6-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h) U-0 — R/W-0 R/W-0 TOUTPS3 TOUTPS2 R/W-0 R/W-0 TOUTPS1 R/W-0 R/W-0 R/W-0 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale 0010 = 1:3 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 0
PIC16F72 7.0 READING PROGRAM MEMORY 7.1 The FLASH Program Memory is readable during normal operation over the entire VDD range. It is indirectly addressed through Special Function Registers (SFR). Up to 14-bit wide numbers can be stored in memory for use as calibration parameters, serial numbers, packed 7-bit ASCII, etc. Executing a program memory location containing data that forms an invalid instruction results in a NOP.
PIC16F72 7.3 Reading the FLASH Program Memory 7.4 To read a program memory location, the user must write two bytes of the address to the PMADRL and PMADRH registers and then set control bit, RD (PMCON1<0>). Once the read control bit is set, the program memory FLASH controller will use the second instruction cycle after to read the data. This causes the second instruction immediately following the “BSF PMCON1,RD” instruction to be ignored.
PIC16F72 8.0 CAPTURE/COMPARE/PWM (CCP) MODULE Additional information on the CCP module is available in the PIC™ Mid-Range MCU Reference Manual, (DS33023). The CCP (Capture/Compare/PWM) module contains a 16-bit register that can operate as a: TABLE 8-1: • 16-bit capture register • 16-bit compare register • PWM master/slave duty cycle register. Table 8-1 shows the timer resources of the CCP Module modes.
PIC16F72 8.1 8.1.2 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge 8.1.1 CCP PIN CONFIGURATION In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit. Note: If the RC2/CCP1 is configured as an output, a write to the port can cause a capture condition.
PIC16F72 8.2 8.2.1 Compare Mode In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is: • Driven High • Driven Low • Remains Unchanged The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the same time, interrupt flag bit CCP1IF is set.
PIC16F72 TABLE 8-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1 Value on all other RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR 0Bh,8Bh INTCON 10Bh,18Bh GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 0000 0000 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 0000 0000 Address 0Ch PIR1 8Ch PIE1 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 0Eh
PIC16F72 8.3 8.3.1 PWM Mode In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. PWM PERIOD The PWM period is specified by writing to the PR2 register.
PIC16F72 Maximum PWM resolution (bits) for a given PWM frequency is calculated using Equation 8-3. EQUATION 8-3: PWM MAX RESOLUTION PWM Maximum Resolution = FOSC log ( FPWM ) log(2) 8.3.3 The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. bits 3. Note: If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared. For a sample PWM period and duty cycle calculation, see the PIC™ Mid-Range MCU Reference Manual (DS33023).
PIC16F72 9.0 9.1 SYNCHRONOUS SERIAL PORT (SSP) MODULE SSP Module Overview The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can operate in one of two modes: 9.2 SPI Mode This section contains register definitions operational characteristics of the SPI module.
PIC16F72 REGISTER 9-1: SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (ADDRESS 94h) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: SPI Data Input Sample Phase bits SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time (Microwire®) SPI Slave mode: SMP must be cleared when SPI is used in Slave mode I2 C mode: This bit must be maintained clear bit 6 CKE: SPI Clock Edge Select bits (Fi
PIC16F72 REGISTER 9-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit In SPI mode: 1 = A new byte is received while the SSPBUF register is still holding the previ
PIC16F72 FIGURE 9-1: SSP BLOCK DIAGRAM (SPI MODE) To enable the serial port, SSP enable bit, SSPEN (SSPCON<5>) must be set. To reset or reconfigure SPI mode, clear bit SSPEN, re-initialize the SSPCON register, and then set bit SSPEN. This configures the SDI, SDO, SCK, and SS pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRISC register) appropriately programmed.
PIC16F72 FIGURE 9-2: SPI MODE TIMING, MASTER MODE SCK (CKP = 0, CKE = 0) SCK (CKP = 0, CKE = 1) SCK (CKP = 1, CKE = 0) SCK (CKP = 1, CKE = 1) bit6 bit7 SDO bit5 bit2 bit3 bit4 bit1 bit0 SDI (SMP = 0) bit7 bit0 SDI (SMP = 1) bit7 bit0 SSPIF FIGURE 9-3: SPI MODE TIMING (SLAVE MODE WITH CKE = 0) SS (optional) SCK (CKP = 0) SCK (CKP = 1) bit7 SDO bit6 bit5 bit2 bit3 bit4 bit1 bit0 SDI (SMP = 0) bit7 bit0 SSPIF FIGURE 9-4: SPI MODE TIMING (SLAVE MODE WITH CKE = 1) SS SCK (CKP =
PIC16F72 9.3 SSP I 2C Mode Operation The SSP module in I 2C mode fully implements all slave functions, except general call support and provides interrupts on START and STOP bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the Standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer. These are the RC3/ SCK/SCL pin, which is the clock (SCL), and the RC4/ SDI/SDA pin, which is the data (SDA).
PIC16F72 In 10-bit Address mode, two address bytes need to be received by the slave device. The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address the first byte would equal ‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs of the address. The sequence of events for 10-bit address is as follows, with steps 7- 9 for slave-transmitter: 1. 2.
PIC16F72 I 2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) FIGURE 9-6: Receiving Address R/W = 0 Receiving Data Receiving Data ACK ACK ACK A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SDA SCL 1 S 2 3 4 5 6 7 9 8 1 2 SSPIF (PIR1<3>) 3 4 5 6 7 8 9 1 2 3 5 4 8 7 6 9 Cleared in software BF (SSPSTAT<0>) P Bus Master terminates transfer SSPBUF register is read SSPOV (SSPCON<6>) Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent.
PIC16F72 9.3.2 MASTER MODE OPERATION 9.3.3 Master mode operation is supported in firmware using interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a RESET or when the SSP module is disabled. The STOP (P) and START (S) bits will toggle, based on the START and STOP conditions. Control of the I 2C bus may be taken when the P bit is set, or the bus is IDLE and both the S and P bits are clear.
PIC16F72 NOTES: DS39597C-page 52 © 2007 Microchip Technology Inc.
PIC16F72 10.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The A/D module has three registers: • A/D Result Register • A/D Control Register 0 • A/D Control Register 1 The analog-to-digital (A/D) converter module has five inputs for the PIC16F72. A device RESET forces all registers to their RESET state. This forces the A/D module to be turned off and any conversion is aborted. The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number.
PIC16F72 REGISTER 10-2: ADCON1: A/D CONTROL REGISTER 1 (ADDRESS 9Fh) U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 PCFG<2:0>: A/D Port Configuration Control bits PCFG2:PCFG0 RA0 RA1 RA2 RA5 RA3 VREF 000 001 010 011 100 101 11x A A A A A A D A A A A A A D A A A A D D D A A A A D D D A VREF A VREF A VREF D VDD RA3 VDD RA3 VDD RA3 VDD A = Analog input D = Digital I/O Legend: R = Readable bit W = Wr
PIC16F72 FIGURE 10-1: A/D BLOCK DIAGRAM CHS2:CHS0 100 RA5/AN4 VAIN 011 (Input Voltage) RA3/AN3/VREF 010 RA2/AN2 A/D Converter 001 RA1/AN1 000 VDD RA0/AN0 000 or 010 or 100 VREF (Reference Voltage) 001 or 011 or 101 PCFG2:PCFG0 FIGURE 10-2: ANALOG INPUT MODEL VDD Rs ANx VA CPIN 5 pF Sampling Switch VT = 0.6 V VT = 0.6 V RIC ≤ 1 k SS RSS CHOLD = DAC capacitance = 51.
PIC16F72 10.1 A/D Acquisition Requirements 10.3 For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 10-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD).
PIC16F72 10.5 A/D Operation During SLEEP 10.6 The A/D module can operate during SLEEP mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed, which eliminates all digital switching noise from the conversion. When the conversion is completed, the GO/DONE bit will be cleared, and the result loaded into the ADRES register.
PIC16F72 NOTES: DS39597C-page 58 © 2007 Microchip Technology Inc.
PIC16F72 11.
PIC16F72 REGISTER 11-1: CONFIGURATION WORD (ADDRESS 2007h)(1) U-1 U-1 U-1 U-1 U-1 U-1 U-1 u-1 U-1 u-1 — — — — — — — BOREN — CP u-1 u-1 u-1 u-1 PWRTEN WDTEN F0SC1 F0SC0 bit13 bit0 bit 13-7 Unimplemented: Read as ‘1’ bit 6 BOREN: Brown-out Reset Enable bit(2) 1 = BOR enabled 0 = BOR disabled bit 5 Unimplemented: Read as ‘1’ bit 4 CP: FLASH Program Memory Code Protection bit 1 = Code protection off 0 = All memory locations code protected bit 3 PWRTEN: Power-up Timer Enable
PIC16F72 11.2 FIGURE 11-2: Oscillator Configurations 11.2.1 OSCILLATOR TYPES The PIC16F72 can be operated in four different Oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: • • • • LP XT HS RC EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor 11.2.2 OSC1 Clock from Ext.
PIC16F72 TABLE 11-2: Osc Type LP XT HS CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR (FOR DESIGN GUIDANCE ONLY) Crystal Freq Typical Capacitor Values Tested: C1 C2 32 kHz 33 pF 33 pF 200 kHz 15 pF 15 pF 200 kHz 56 pF 56 pF 1 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF 8 MHz 15 pF 15 pF 20 MHz 15 pF 15 pF 11.2.3 For timing insensitive applications, the “RC” device option offers additional cost savings.
PIC16F72 FIGURE 11-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External RESET MCLR SLEEP WDT Module WDT Time-out Reset VDD Rise Detect Power-on Reset VDD Brown-out Reset S BOREN OST/PWRT OST Chip_Reset 10-bit Ripple Counter R Q OSC1 (1) On-chip RC OSC PWRT 10-bit Ripple Counter Enable PWRT Enable OST Note 11.4 1: This is a separate oscillator from the RC oscillator of the CLKI pin. MCLR PIC16F72 device has a noise filter in the MCLR Reset path.
PIC16F72 11.5 Power-on Reset (POR) A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.2V - 1.7V). To take advantage of the POR, tie the MCLR pin to VDD, as described in Section 11.4. A maximum rise time for VDD is specified. See Section 14.0, Electrical Characteristics for details. When the device starts normal operation (exits the RESET condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure operation.
PIC16F72 TABLE 11-3: TIME-OUT IN VARIOUS SITUATIONS Power-up Oscillator Configuration Brown-out Wake-up from SLEEP PWRTEN = 0 PWRTEN = 1 XT, HS, LP 72 ms + 1024 TOSC 1024 TOSC 72 ms + 1024 TOSC 1024 TOSC RC 72 ms — 72 ms — TABLE 11-4: STATUS BITS AND THEIR SIGNIFICANCE BOR TO PD POR (PCON<1>) (PCON<0>) (STATUS<4>) (STATUS<3>) Significance 0 x 1 1 Power-on Reset 0 x 0 x Illegal, TO is set on POR 0 x x 0 Illegal, PD is set on POR u 0 1 1 Brown-out Reset u u 0 1 WDT
PIC16F72 TABLE 11-6: Register W INITIALIZATION CONDITIONS FOR ALL REGISTERS Power-on Reset, Brown-out Reset xxxx xxxx MCLR Reset, WDT Reset uuuu uuuu INDF N/A N/A TMR0 xxxx xxxx uuuu uuuu 0000h 0000h PCL Wake-up via WDT or Interrupt uuuu uuuu N/A uuuu uuuu PC + 1(2) (3) STATUS 0001 1xxx 000q quuu uuuq quuu(3) FSR xxxx xxxx uuuu uuuu uuuu uuuu PORTA --0x 0000 --0u 0000 --uu uuuu PORTB xxxx xxxx uuuu uuuu uuuu uuuu PORTC xxxx xxxx uuuu uuuu uuuu uuuu PCLATH ---0 0000 ---0 0
PIC16F72 FIGURE 11-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH PULL-UP RESISTOR) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 11-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH RC NETWORK): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 11-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH RC NETWORK): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTER
PIC16F72 FIGURE 11-9: SLOW RISE TIME (MCLR TIED TO VDD THROUGH RC NETWORK) 5V VDD 1V 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 11.11 Interrupts The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. The PIC16F72 has up to eight sources of interrupt. The interrupt control register (INTCON) records individual interrupt requests in flag bits.
PIC16F72 11.11.1 INT INTERRUPT 11.11.3 External interrupt on the RB0/INT pin is edge triggered, either rising, if bit INTEDG (OPTION<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt.
PIC16F72 11.13 Watchdog Timer (WDT) The Watchdog Timer is a free running, on-chip RC oscillator that does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKI pin. That means that the WDT will run, even if the clock on the OSC1/CLKI and OSC2/ CLKO pins of the device has been stopped, for example, by execution of a SLEEP instruction. WDT time-out period values may be found in the Electrical Specifications section under parameter #31.
PIC16F72 11.14 Power-down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low, or hi-impedance).
PIC16F72 FIGURE 11-12: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKO(4) INT pin INTF Flag (INTCON<1>) Interrupt Latency (Note 2) GIE bit (INTCON<7>) Processor in SLEEP INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: PC PC+1 Inst(PC) = SLEEP Inst(PC + 1) PC+2 Inst(PC + 2) PC+2 Inst(PC - 1) SLEEP Inst(PC + 1) PC + 2 Dummy cycle 0004h 0005h Inst(0004h) Inst(0005h) Dummy
PIC16F72 12.0 INSTRUCTION SET SUMMARY Each PIC16F72 instruction is a 14-bit word divided into an OPCODE that specifies the instruction type and one or more operands that further specify the operation of the instruction. The PIC16F72 instruction set summary in Table 12-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 12-1 shows the opcode field descriptions. For byte-oriented instructions, ‘f’ represents a file register designator and ‘d’ represents a destination designator.
PIC16F72 TABLE 12-2: Mnemonic, Operands PIC16F72 INSTRUCTION SET Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f
PIC16F72 12.1 Instruction Descriptions ADDLW Add Literal and W ANDWF AND W with f Syntax: [ label ] ADDLW Syntax: [ label ] ANDWF Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) + k → (W) Status Affected: C, DC, Z Operation: (W) .AND. (f) → (destination) The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register. Status Affected: Z Description: AND the W register with register ‘f’.
PIC16F72 BTFSS Bit Test f, Skip if Set CLRF Clear f Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRF Operands: 0 ≤ f ≤ 127 0≤b<7 Operands: 0 ≤ f ≤ 127 Operation: Operation: skip if (f) = 1 00h → (f) 1→Z Status Affected: None Status Affected: Z Description: If bit ‘b’ in register ‘f’ = ‘0’, the next instruction is executed. If bit ‘b’ = ‘1’, then the next instruction is discarded and a NOP is executed instead, making this a 2 TCY instruction.
PIC16F72 COMF Complement f Syntax: [ label ] COMF GOTO Unconditional Branch Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ k ≤ 2047 Operation: (f) → (destination) Operation: k → PC<10:0> PCLATH<4:3> → PC<12:11> Status Affected: Z Status Affected: None Description: The contents of register ‘f’ are complemented. If ‘d’ = ‘0’, the result is stored in W. If ‘d’ = ‘1’, the result is stored back in register ‘f’. Description: GOTO is an unconditional branch.
PIC16F72 IORLW Inclusive OR Literal with W MOVLW Move Literal to W Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255 Operation: (W) .OR. k → (W) Operation: k → (W) Status Affected: Z Status Affected: None Description: The contents of the W register are OR’d with the eight-bit literal ‘k’. The result is placed in the W register. Description: The eight-bit literal ‘k’ is loaded into W register. The don’t cares will assemble as ‘0’s.
PIC16F72 RETFIE Return from Interrupt RLF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] Operands: None Operands: Operation: TOS → PC, 1 → GIE 0 ≤ f ≤ 127 d ∈ [0,1] Operation: See description below Status Affected: None Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry Flag. If ‘d’ = ‘0’, the result is placed in the W register. If ‘d’ = ‘1’, the result is stored back in register ‘f’.
PIC16F72 SUBLW Syntax: Subtract W from Literal [ label ] SUBLW k XORLW Exclusive OR Literal with W Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255 Operation: k - (W) → (W) XORLW k Operation: (W) .XOR. k → (W) Status Affected: C, DC, Z Status Affected: Z Description: The W register is subtracted (2’s complement method) from the eight-bit literal ‘k’. The result is placed in the W register.
PIC16F72 13.
PIC16F72 13.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can also link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for precompiled code to be used with the MPLINK object linker.
PIC16F72 13.8 MPLAB ICD In-Circuit Debugger Microchip's In-Circuit Debugger, MPLAB ICD, is a powerful, low cost, run-time development tool. This tool is based on the FLASH PIC MCUs and can be used to develop for this and other PIC microcontrollers. The MPLAB ICD utilizes the in-circuit debugging capability built into the FLASH devices.
PIC16F72 13.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board The PICDEM 3 demonstration board is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Module. All the necessary hardware and software is included to run the basic demonstration programs.
Software Tools Programmers Debugger Emulators PIC12CXXX PIC14000 PIC16C5X PIC16C6X PIC16CXXX PIC16F62X PIC16C7X 9 9 9 9 9 9 © 2007 Microchip Technology Inc. 9 9 9 † † 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 MCP2510 * Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB® ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77.
PIC16F72 NOTES: DS39597C-page 86 © 2007 Microchip Technology Inc.
PIC16F72 14.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Ambient temperature under bias................................................................................................................ -55 to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4) ......................................... -0.
PIC16F72 FIGURE 14-1: PIC16F72 (INDUSTRIAL, EXTENDED) VOLTAGE-FREQUENCY GRAPH 6.0V 5.5V 5.0V Voltage 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 16 MHz 20 MHz Frequency FIGURE 14-2: PIC16LF72 (INDUSTRIAL) VOLTAGE-FREQUENCY GRAPH 6.0V 5.5V Voltage 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 4 MHz 10 MHz Frequency FMAX = (12 MHz/V) (VDDAPPMIN - 2.5V) + 4 MHz Note 1: VDDAPPMIN is the minimum voltage of the PIC® device in the application. Note 2: FMAX has a maximum frequency of 10 MHz.
PIC16F72 14.1 DC Characteristics: PIC16F72 (Industrial, Extended) PIC16LF72 (Industrial) PIC16LF72 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F72 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Sym VDD Characteristic Min Typ† Max Units Supply Voltage D001 D001 D001A PIC16LF72 2.
PIC16F72 14.1 DC Characteristics: PIC16F72 (Industrial, Extended) PIC16LF72 (Industrial) (Continued) PIC16LF72 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F72 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F72 14.2 DC Characteristics: PIC16F72 (Industrial, Extended) PIC16LF72 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Operating voltage VDD range as described in DC Specification, Section 14.1. DC CHARACTERISTICS Param No.
PIC16F72 14.2 DC Characteristics: PIC16F72 (Industrial, Extended) PIC16LF72 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Operating voltage VDD range as described in DC Specification, Section 14.1. DC CHARACTERISTICS Param No. Sym Min Typ† Max Units D080 Output Low Voltage I/O ports — — 0.6 V D083 OSC2/CLKO (RC osc config) — — 0.
PIC16F72 14.3 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
PIC16F72 FIGURE 14-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 14-1: Parameter No. EXTERNAL CLOCK TIMING REQUIREMENTS Symbol FOSC Characteristic External CLKI Frequency (Note 1) Oscillator Frequency (Note 1) 1 TOSC External CLKI Period (Note 1) Oscillator Period (Note 1) Min Typ† Max Units Conditions DC — 1 MHz XT Osc mode DC — 20 MHz HS Osc mode DC — 32 kHz DC — 4 MHz RC osc mode LP Osc mode 0.
PIC16F72 FIGURE 14-5: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 14 19 12 18 16 I/O Pin (Input) 15 17 I/O Pin (Output) New Value Old Value 20, 21 Note: Refer to Figure 14-3 for load conditions. TABLE 14-2: CLKO AND I/O TIMING REQUIREMENTS Param No.
PIC16F72 FIGURE 14-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer Reset 31 34 34 I/O Pins Note: Refer to Figure 14-3 for load conditions. FIGURE 14-7: BROWN-OUT RESET TIMING VBOR VDD 35 TABLE 14-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter No.
PIC16F72 FIGURE 14-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 14-3 for load conditions. TABLE 14-4: Param No.
PIC16F72 FIGURE 14-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1 ) RC2/CCP1 (Capture Mode) 50 51 52 RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 14-3 for load conditions. TABLE 14-5: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1) Param Symbol No. 50* TccL Characteristic Min No Prescaler 0.5 TCY + 20 — — ns Standard(F) 10 — — ns Extended(LF) 20 — — ns CCP1 input high No Prescaler time Standard(F) With Prescaler Extended(LF) 0.
PIC16F72 FIGURE 14-10: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 Bit6 - - - - - -1 MSb SDO LSb 75, 76 SDI MSb In Bit6 - - - -1 LSb In 74 73 Note: Refer to Figure 14-3 for load conditions. FIGURE 14-11: SPI MASTER MODE TIMING (CKE = 1, SMP = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb Bit6 - - - - - -1 LSb Bit6 - - - -1 LSb In 75, 76 SDI MSb In 74 Note: Refer to Figure 14-3 for load conditions.
PIC16F72 FIGURE 14-12: SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO LSb Bit6 - - - - - -1 77 75, 76 SDI MSb In Bit6 - - - -1 LSb In 74 73 Note: Refer to Figure 14-3 for load conditions. FIGURE 14-13: SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 SDO MSb Bit6 - - - - - -1 LSb 75, 76 SDI MSb In 77 Bit6 - - - -1 LSb In 74 Note: Refer to Figure 14-3 for load conditions.
PIC16F72 TABLE 14-6: Param No.
PIC16F72 TABLE 14-7: Param No.
PIC16F72 TABLE 14-8: Param No. 100* I2C BUS DATA REQUIREMENTS Symbol THIGH Characteristic Clock High Time Min Max Units 100 kHz mode 4.0 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — μs Device must operate at a minimum of 10 MHz 1.5 TCY — 100 kHz mode 4.7 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — μs Device must operate at a minimum of 10 MHz SSP Module 101* TLOW Clock Low Time 1.5 TCY — — 1000 ns 20 + 0.
PIC16F72 TABLE 14-9: Param No. A01 A/D CONVERTER CHARACTERISTICS: PIC16F72 (INDUSTRIAL) PIC16LF72 (INDUSTRIAL) Sym NR Characteristic Resolution Min Typ† Max Units Conditions PIC16F72 — — 8 bits bit VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF PIC16LF72 — — 8 bits bit VREF = VDD = 2.2V A02 EABS Total Absolute Error — — <±1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A03 EIL Integral Linearity Error — — <±1 LSb VREF = VDD = 5.
PIC16F72 FIGURE 14-16: A/D CONVERSION TIMING BSF ADCON0, GO 134 1 TCY (TOSC/2)(1) 131 Q4 130 A/D CLK 132 7 A/D DATA 6 5 4 3 2 1 0 NEW_DATA OLD_DATA ADRES ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 14-10: A/D CONVERSION REQUIREMENTS Param Sym No.
PIC16F72 NOTES: DS39597C-page 106 © 2007 Microchip Technology Inc.
PIC16F72 15.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
PIC16F72 FIGURE 15-3: TYPICAL IDD vs. FOSC OVER VDD (XT MODE) 0.9 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 0.8 5.5V 0.7 5.0V 0.6 IDD (mA) 4.5V 0.5 4.0V 3.5V 0.4 3.0V 0.3 2.5V 2.0V 0.2 0.1 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 3.5 4.0 FOSC (MHz) MAXIMUM IDD vs. FOSC OVER VDD (XT MODE) FIGURE 15-4: 1.2 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 1.
PIC16F72 FIGURE 15-5: TYPICAL IDD vs. FOSC OVER VDD (LP MODE) 55 IDD (μA) 50 45 5.5V 40 5.0V 35 4.5V 4.0V 30 3.5V 25 3.0V 20 2.5V 2.0V 15 10 30 40 50 60 70 80 90 80 90 100 FOSC (kHz) FIGURE 15-6: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE) 100 90 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 5.5V 80 5.0V 70 IDD (μA) 4.5V 60 4.0V 50 3.5V 40 3.0V 2.5V 30 2.
PIC16F72 FIGURE 15-7: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 20 pF, 25°C) 5.0 4.5 Operation above 4 MHz is not recomended 4.0 3.5 10 kΩ Freq (MHz) 3.0 2.5 2.0 1.5 1.0 100 kΩ 0.5 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-8: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 100 pF, 25°C) 5.0 Operation above 4 MHz is not recomended 4.0 5.1 kΩ Freq (MHz) 3.0 10 kΩ 2.0 1.0 100 kΩ 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16F72 FIGURE 15-9: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 300 pF, 25°C) 300 250 3.3 kΩ 200 Freq (kHz) 5.1 kΩ 150 10 kΩ 100 50 100 kΩ 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-10: IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) 100 Max 125°C 10 IPD (uA) Max 85°C 1 Typ 25°C 0.1 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 0.01 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16F72 FIGURE 15-11: ΔIBOR vs. VDD OVER TEMPERATURE 1,000 Max (125˚C) Typ (25˚C) Device in SLEEP Indeterminant State IDD (μA) Device in RESET 100 Note: Device current in RESET depends on Oscillator mode, frequency and circuit. Max (125˚C) Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) Typ (25˚C) 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.0 5.5 VDD (V) FIGURE 15-12: TYPICAL AND MAXIMUM ΔIWDT vs.
PIC16F72 FIGURE 15-13: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40°C TO +125°C) 16F77 50 45 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 40 35 WDT Period (ms) Max (125°C) 30 25 Typ (25°C) 20 Min (-40°C) 15 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-14: AVERAGE WDT PERIOD vs.
PIC16F72 FIGURE 15-15: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40°C TO +125°C) 5.5 5.0 4.5 4.0 Max 3.5 VOH (V) Typ (25°C) 3.0 2.5 Min 2.0 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 1.5 1.0 0.5 0.0 0 5 10 15 20 25 IOH (-mA) FIGURE 15-16: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40°C TO +125°C) 3.
PIC16F72 FIGURE 15-17: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 5V, -40°C TO +125°C) 1.0 0.9 Max (125°C) Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 0.8 0.7 Max (85°C) VOL (V) 0.6 0.5 Typ (25°C) 0.4 0.3 Min (-40°C) 0.2 0.1 0.0 0 5 10 15 20 25 IOL (-mA) FIGURE 15-18: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 3V, -40°C TO +125°C) 3.
PIC16F72 FIGURE 15-19: MINIMUM AND MAXIMUM VIN vs. VDD, (TTL INPUT, -40°C TO +125°C) 1.5 1.4 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 1.3 VTH Max (-40°C) 1.2 1.1 VIN (V) VTH Typ (25°C) 1.0 VTH Min (125°C) 0.9 0.8 0.7 0.6 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-20: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40°C TO +125°C) 4.
PIC16F72 16.0 PACKAGE MARKING INFORMATION 28-Lead PDIP (Skinny DIP) Example PIC16F72-I/SP e3 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SSOP PIC16F72-I/SO e3 0710017 Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 28-Lead QFN PIC16F72 -I/SS e3 0720017 Example XXXXXXXX XXXXXXXX YYWWNNN PIC16F72 -I/ML e3 0710017 Legend: XX...
PIC16F72 28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 28 Pitch e Top to Seating Plane A – – .200 Molded Package Thickness A2 .120 .135 .150 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .
PIC16F72 28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 3 b e h α A2 A h c φ L A1 Units Dimension Limits Number of Pins β L1 MILLMETERS MIN N NOM MAX 28 Pitch e Overall Height A – 1.27 BSC – Molded Package Thickness A2 2.05 – – Standoff § A1 0.10 – 0.30 Overall Width E Molded Package Width E1 7.
PIC16F72 28-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 1 2 NOTE 1 b e c A2 A φ A1 L L1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 28 Pitch e Overall Height A – 0.65 BSC – 2.00 Molded Package Thickness A2 1.65 1.75 1.85 Standoff A1 0.05 – – Overall Width E 7.40 7.80 8.
PIC16F72 28-Lead Plastic Quad Flat, No Lead Package (ML) – 6x6 mm Body [QFN] with 0.55 mm Contact Length Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D2 EXPOSED PAD e E b E2 2 2 1 1 N K N NOTE 1 L BOTTOM VIEW TOP VIEW A A3 A1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 28 Pitch e Overall Height A 0.80 0.65 BSC 0.90 1.00 Standoff A1 0.00 0.02 0.
PIC16F72 NOTES: DS39597C-page 122 © 2007 Microchip Technology Inc.
PIC16F72 APPENDIX A: REVISION HISTORY Revision C (January 2007) This revision includes updates to the packaging diagrams. Revision A (April 2002) This is a new data sheet. However, this device is similar to the PIC16C72 device found in the PIC16C7X Data Sheet (DS30390), the PIC16C72A Data Sheet (DS35008) or the PIC16F872 device (DS30221). Revision B (May 2002) Final data sheet. Includes device characterization data. Minor typographic revisions throughout.
PIC16F72 NOTES: DS39597C-page 124 © 2007 Microchip Technology Inc.
PIC16F72 INDEX A C A/D Capture/Compare/PWM ..................................................... 37 Associated Registers with PWM and Timer2.............. 42 Associated Registers, Capture, Compare and Timer1............................................................. 40 Capture CCP1IF............................................................... 38 CCPR1 ............................................................... 38 CCPR1H:CCPR1L.............................................. 38 Capture Mode........
PIC16F72 F FLASH Program Memory Associated Registers .................................................. 28 Operation During Code Protect................................... 28 Reading....................................................................... 28 FSR Register................................................................... 9, 10 I I/O Ports .............................................................................. 21 PORTA ....................................................................
PIC16F72 Oscillator Configuration................................................. 59, 61 Crystal Oscillator/Ceramic Resonators ....................... 61 HS ......................................................................... 61, 65 LP.......................................................................... 61, 65 RC................................................................... 61, 62, 65 XT ......................................................................... 61, 65 Oscillator, WDT ........
PIC16F72 Registers ............................................................................. 36 ADCON0 (A/D Control 0) ............................................ 53 ADCON1 (A/D Control 1) ............................................ 54 CCPCON1 (Capture/Compare/PWM Control 1) ......... 37 Initialization Conditions (table) .................................... 66 INTCON (Interrupt Control) ......................................... 14 OPTION ................................................................
PIC16F72 Timing Diagrams A/D Conversion......................................................... 105 Brown-out Reset ......................................................... 96 Capture/Compare/PWM (CCP1)................................. 98 CLKO and I/O ............................................................. 95 External Clock............................................................. 94 I2C Bus Data ............................................................. 102 I2C Bus START/STOP bits............
PIC16F72 NOTES: DS39597C-page 130 © 2007 Microchip Technology Inc.
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PIC16F72 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device * X Temperature Range /XX XXX Package Pattern Device PIC16F72: Standard VDD range PIC16F72T: (Tape and Reel) PIC16LF72: Extended VDD range Temperature Range I Package SO SS ML P Pattern QTP, SQTP, ROM Code (factory specified) or Special Requirements. Blank for OTP and Windowed devices.
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