Datasheet

© 2007 Microchip Technology Inc. DS41206B-page 71
PIC16F716
FIGURE 9-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
FIGURE 9-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR
NOT TIED TO VDD): CASE 1
FIGURE 9-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR
NOT TIED TO VDD): CASE 2
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST