Datasheet

PIC16F716
DS41206B-page 60 © 2007 Microchip Technology Inc.
TABLE 8-6: REGISTERS ASSOCIATED WITH PWM
REGISTER 8-3: PWM1CON: ENHANCED PWM CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 PRSEN: PWM Restart Enable bit
1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes
away; the PWM restarts automatically
0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM
bit 6-0 PDC<6:0>: PWM Delay Count bits
PDCn = Number of F
OSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal
should transition active and the actual time it transitions active
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on
all other
Resets
CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx xxxx xxxx
CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx xxxx xxxx
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
ECCPAS ECCPASE ECCPAS2
— ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 00-0 0000 00-0 0000
INTCON GIE PEIE
T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
PIE1
— ADIE — — — CCP1IE TMR2IE TMR1IE -0-- -000 -0-- -000
PIR1
— ADIF — — — CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- -000
PR2 Timer2 Period Register 1111 1111 1111 1111
PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 0000 0000
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx xxxx xxxx
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx xxxx xxxx
TMR2 Timer2 Module’s Register 0000 0000 0000 0000
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the PWM.