Datasheet

© 2007 Microchip Technology Inc. DS41206B-page 105
PIC16F716
FIGURE 12-10: A/D CONVERSION TIMING
TABLE 12-8: A/D CONVERSION REQUIREMENTS
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
130 T
AD A/D clock period Industrial 1.6 — — μsTOSC based, VREF ≥ 3.0V
Industrial 1.6 4.0 6.0 μs A/D RC mode
Extended 1.6 — — μsT
OSC based, VREF ≥ 3.0V
Extended 1.6 6.0 9.0 μs A/D RC mode
131 T
CNV Conversion time (not including S/H time)
(1)
9.5 — 9.5 TAD
132 TACQ Acquisition time (Note 2)
5*
20
—
—
—
μs
μs The minimum time is the amplifier
settling time. This may be used if
the “new” input voltage has not
changed by more than 1 LSb (i.e.,
20.0 mV @ 5.12V) from the last
sampled voltage (as stated on
C
HOLD).
134 T
GO Q4 to A/D clock start — TOSC/2 ** — — If the A/D clock source is selected
as RC, a time of T
CY is added
before the A/D clock starts. This
allows the SLEEP instruction to be
executed.
135 T
SWC Switching from convert → sample time 1.5 ** — — TAD
* These parameters are characterized but not tested.
** This specification ensured by design.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRES register may be read on the following T
CY cycle.
2: See Section 12.1 “DC Characteristics: PIC16F716 (Industrial, Extended)” for min. conditions.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(T
OSC/2)
(1)
7 6 5432 10
Note 1: If the A/D clock source is selected as RC, a time of T
CY is added before the A/D clock starts. This allows the SLEEP instruction
to be executed.
1 Tcy
134