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PIC16F716

Data Sheet

8-bit Flash-based Microcontroller

with A/D Converter and

Enhanced Capture/Compare/PWM

Summary of content (136 pages)

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PIC16F716 Data Sheet 8-bit Flash-based Microcontroller with A/D Converter and Enhanced Capture/Compare/PWM © 2007 Microchip Technology Inc.
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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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PIC16F716 8-bit Flash-based Microcontroller with A/D Controller and Enhanced Capture/Compare PWM Microcontroller Core Features: Low-Power Features: • High-performance RISC CPU • Only 35 single-word instructions to learn - All single-cycle instructions except for program branches which are two-cycle • Operating speed: DC – 20 MHz clock input DC – 200 ns instruction cycle • Interrupt capability (up to 7 internal/external interrupt sources) • 8-level deep hardware stack • Direct, Indirect and Relative Addres
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PIC16F716 18-Pin Diagram 18-pin PDIP, SOIC TABLE 1: 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 PIC16F716 RA2/AN2 RA3/AN3/VREF RA4/T0CKI MCLR/VPP VSS RB0/INT/ECCPAS2 RB1/T1OSO/T1CKI RB2/T1OSI RB3/CCP1/P1A RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT VDD RB7/P1D RB6/P1C RB5/P1B RB4/ECCPAS0 18-PIN PDIP, SOIC SUMMARY I/O Pin Analog ECCP Timer Interrupts Pull-ups Basic RA0 17 AN0 — — — — — RA1 18 AN1 — — — — — RA2 1 AN2 — — — — — RA3 2 AN3/VREF — — — — — RA4 3 — —
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PIC16F716 20-Pin Diagram 20-pin SSOP TABLE 2: I/O 20 19 18 17 16 15 14 13 12 11 PIC16F716 1 2 3 4 5 6 7 8 9 10 RA2/AN2 RA3/AN3/VREF RA4/T0CKI MCLR/VPP VSS VSS RB0/INT/ECCPAS2 RB1/T1OSO/T1CKI RB2/T1OSI RB3/CCP1/P1A RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT VDD VDD RB7/P1D RB6/P1C RB5/P1B RB4/ECCPAS0 20-PIN SSOP SUMMARY Pin Analog ECCP Timer Interrupts Pull-ups Basic RA0 19 AN0 — — — — — RA1 20 AN1 — — — — — RA2 — — — — 1 AN2 — RA3 2 AN3/VREF — — — — — RA4 3 — —
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PIC16F716 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Memory Organization ................................................................................................................................................................... 7 3.0 I/O Ports .......................................................................................
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PIC16F716 1.0 DEVICE OVERVIEW This document contains device specific information for the PIC16F716. Figure 1-1 is the block diagram for the PIC16F716 device. The pinouts are listed in Table 1-1.
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PIC16F716 TABLE 1-1: PIC16F716 PINOUT DESCRIPTION Name Function Input Type Output Type Description Master clear (Reset) input. This pin is an active-low Reset to the device. MCLR/VPP MCLR VPP P — Programming voltage input OSC1/CLKIN OSC1 XTAL — Oscillator crystal input CLKIN CMOS — External clock source input CLKIN ST — RC Oscillator mode OSC2 XTAL — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode.
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PIC16F716 2.0 MEMORY ORGANIZATION There are two memory blocks in the PIC16F716 device. Each block (program memory and data memory) has its own bus so that concurrent access can occur. 2.1 Program Memory Organization The PIC16F716 has a 13-bit program counter capable of addressing an 8K x 14 program memory space. The PIC16F716 has 2K x 14 words of program memory. Accessing a location above the physically implemented address will cause a wrap-around.
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PIC16F716 2.2.1 GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly or indirectly through the File Select Register FSR (Section 2.5 “Indirect Addressing, INDF and FSR Registers”).
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PIC16F716 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is give in Table 2-1. The Special Function Registers can be classified into two sets; core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section.
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PIC16F716 TABLE 2-2: Address SPECIAL FUNCTION REGISTER SUMMARY BANK 1 Name 80h INDF(1) 81h OPTION_REG 82h PCL(1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter’s (PC) Least Significant Byte 0000 0000 18 1111 1111 12 0000 0000 17 83h STATUS(1) FSR(1) 85h TRISA — — —(7) TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 19
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PIC16F716 2.2.2.1 STATUS Register The STATUS register, shown in Register 2-1, contains the arithmetic status of the ALU, the Reset status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
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PIC16F716 2.2.2.2 OPTION Register Note: The OPTION register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 2-2: To achieve a 1:1 prescaler assignment for the Timer0 register, assign the prescaler to the Watchdog Timer.
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PIC16F716 2.2.2.3 INTCON Register Note: The INTCON Register is a readable and writable register which contains various enable and flag bits for the TMR0 register overflow, RB Port change and external RB0/INT pin interrupts. REGISTER 2-3: R/W-0 INTCON: INTERRUPT CONTROL REGISTER R/W-0 GIE Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register.
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PIC16F716 2.2.2.4 PIE1 Register Note: This register contains the individual enable bits for the peripheral interrupts. REGISTER 2-4: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
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PIC16F716 2.2.2.5 PIR1 Register This register contains the individual flag bits for the peripheral interrupts. REGISTER 2-5: Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
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PIC16F716 2.2.2.6 PCON Register Note: The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR) to an external MCLR Reset or WDT Reset. These devices contain an additional bit to differentiate a Brown-out Reset condition from a Power-on Reset condition. If the BOREN Configuration bit is set, BOR is ‘1’ on Power-on Reset and reset to ‘0’ when a Brown-out condition occurs.
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PIC16F716 2.3 PCL and PCLATH The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-3 shows the two situations for the loading of the PC. The upper example in Figure 2-3 shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH).
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PIC16F716 2.5 Indirect Addressing, INDF and FSR Registers EXAMPLE 2-2: The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.
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PIC16F716 3.0 I/O PORTS Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. 3.1 PORTA and the TRISA Register PORTA is a 5-bit wide bidirectional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a High-impedance mode).
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PIC16F716 FIGURE 3-2: BLOCK DIAGRAM OF RA4/T0CKI PIN Data Latch DATA BUS Q D WR PORT CK RA4/T0CKI Q N TRIS Latch WR TRIS VSS Q D CK VSS Schmitt Trigger Input Buffer Q RD TRIS Q D ENEN RD PORT Timer0 Clock Input TABLE 3-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Value on all other Resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR PORTA — — — RA4 RA3 RA2 RA1 RA0 ---x 0000 ---u uuuu TRISA — — — ADCON1 — — — Name TRISA4 TRISA3 TRISA2
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PIC16F716 3.2 PORTB and the TRISB Register PORTB is an 8-bit wide bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin).
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PIC16F716 FIGURE 3-4: BLOCK DIAGRAM OF RB1/T1OSO/T1CKI PIN VDD T1OSCEN RBPU(1) weak P pull-up VDD DATA BUS WR PORTB Data Latch D CK RB1/T1OSO/T1CKI Q Q TRIS Latch D WR TRISB CK VSS Q Q RD TRISB T1OSCEN TTL Buffer Q D EN RD PORTB T1OSI (From RB2) TMR1 oscillator To Timer1 clock input ST Buffer Note FIGURE 3-5: 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION register).
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PIC16F716 FIGURE 3-6: BLOCK DIAGRAM OF RB3/CCP1/P1A PIN VDD RBPU(1) [PWMA(P1A) / CCP1 Compare] Output Enable [PWMA(P1A) / CCP1 Compare] Output weak P pull-up VDD 1 RB3/CCP1/P1A 0 PWMA(P1A) Auto-shutdown tri-state VSS Data Latch DATA BUS D WR PORTB CK Q Q TRIS Latch D WR TRISB CK Q Q RD TRIS TTL Buffer Q D EN RD PORTB Schmitt Trigger Buffer CCP – Capture input Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION register).
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PIC16F716 FIGURE 3-8: BLOCK DIAGRAM OF RB5/P1B PIN VDD RBPU(1) PWMB(P1B) Enable PWMB(P1B) Data out PWMB(P1B) Auto-shutdown tri-state Data Latch DATA BUS D Q WR PORTB weak P pull-up VDD 1 RB5/P1B 0 CK TRIS Latch D Q WR TRISB CK VSS TTL Buffer Q RD TRISB Q Latch D EN RD PORTB Q1 Set RBIF Q From other RB<7:4> pins D RD PORTB Q3 EN Note FIGURE 3-9: 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION register).
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PIC16F716 FIGURE 3-10: BLOCK DIAGRAM OF RB7/P1D PIN VDD RBPU(1) PWMD(P1D) Enable PWMD(P1D) Data out PWMD(P1D) Auto-shutdown tri-state Data Latch DATA BUS D Q WR PORTB weak P pull-up VDD 1 RB7/P1D 0 CK TRIS Latch D Q WR TRISB CK VSS Q TTL Buffer ST Buffer RD TRISB Q Latch D EN RD PORTB Q1 Set RBIF Q From other RB<7:4> pins D Note RD PORTB Q3 EN ICSPD – In-Circuit Serial Programming™ Data Input TABLE 3-2: 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU
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PIC16F716 4.0 TIMER0 MODULE 4.1 Timer0 Operation The Timer0 module is an 8-bit timer/counter with the following features: When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter. • • • • • 4.1.
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PIC16F716 4.1.3 SOFTWARE PROGRAMMABLE PRESCALER When changing the prescaler assignment from the WDT to the Timer0 module, the following instruction sequence must be executed (see Example 4-2). A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’.
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PIC16F716 5.0 TIMER1 MODULE WITH GATE CONTROL The Timer1 module is a 16-bit timer/counter with the following features: • • • • • • • 16-bit timer/counter register pair (TMR1H:TMR1L) Programmable internal or external clock source 3-bit prescaler Optional LP oscillator Synchronous or asynchronous operation Interrupt on overflow Wake-up on overflow (external clock, Asynchronous mode only) • Time base for the Capture/Compare function • Special Event Trigger (with ECCP) 5.
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PIC16F716 5.3 Timer1 Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. 5.4 Timer1 Oscillator A low-power 32.768 kHz crystal oscillator is built-in between pins T1OSI (input) and T1OSO (output).
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PIC16F716 5.8 ECCP Capture/Compare Time Base The ECCP module uses the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode. In Capture mode, the value in the TMR1H:TMR1L register pair is copied into the CCPR1H:CCPR1L register pair on a configured event. In Compare mode, an event is triggered when the value CCPR1H:CCPR1L register pair matches the value in the TMR1H:TMR1L register pair. This event can be a Special Event Trigger. For more information, see Section 8.
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PIC16F716 5.10 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register 5-1, is used to control Timer1 and select the various features of the Timer1 module.
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PIC16F716 TABLE 5-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Name Bit 7 INTCON Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets 0000 000x GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x PIE1 — ADIE — — — CCP1IE TMR2IE TMR1IE -0-- -000 -0-- -000 PIR1 — ADIF — — — CCP1IF TMR2IF TMR1IF -0-- -000 -0-- -000 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1L Holding R
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PIC16F716 6.0 TIMER2 MODULE The Timer2 module is an 8-bit timer with the following features: • • • • • 8-bit timer register (TMR2) 8-bit period register (PR2) Interrupt on TMR2 match with PR2 Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘1’. Timer2 is turned off by clearing the TMR2ON bit to a ‘0’. The Timer2 prescaler is controlled by the T2CKPS bits in the T2CON register.
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PIC16F716 REGISTER 6-1: T2CON: TIMER 2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 = 1:1 Postscaler 0001 = 1:2 Postscaler 0010 = 1:3 Postscaler 0011 = 1:4 Postscaler
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PIC16F716 7.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The ADC voltage reference is software selectable to either VDD or a voltage applied to the external reference pins. The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 8-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter.
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PIC16F716 7.1 ADC Configuration 7.1.3 When configuring and using the ADC the following functions must be considered: • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control 7.1.1 Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. CHANNEL SELECTION The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit.
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PIC16F716 7.1.5 INTERRUPTS The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC interrupt flag is the ADIF bit in the PIR1 register. The ADC interrupt enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. Note: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled.
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PIC16F716 7.2 7.2.1 ADC Operation STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion. Note: 7.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 7.2.6 “A/D Conversion Procedure”.
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PIC16F716 7.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC.
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PIC16F716 REGISTER 7-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 PCFG<2:0>: A/D Port Configuration Control bits.
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PIC16F716 7.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 7-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 7-2.
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PIC16F716 FIGURE 7-2: ANALOG INPUT MODEL VDD Rs ANx CPIN 5 pF VA VT = 0.6V VT = 0.6V RIC ≤ 1k Sampling Switch SS Rss ILEAKAGE(1) CHOLD = 10 pF VSS Legend: CPIN = Input Capacitance = Threshold Voltage VT I LEAKAGE = Leakage current at the pin due to various junctions RIC = Interconnect Resistance SS = Sampling Switch CHOLD = Sample/Hold Capacitance Note 1: 6V 5V VDD 4V 3V 2V RSS 5 6 7 8 9 10 11 Sampling Switch (kΩ) See Section 12.0 “Electrical Characteristics”.
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PIC16F716 TABLE 7-2: Name ADCON0 ADCON1 ADRES SUMMARY OF ASSOCIATED ADC REGISTERS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 0000 0000 0000 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000 xxxx xxxx uuuu uuuu A/D Result Register GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x PIE1 — ADIE — — — CCP1IE TMR2IE TMR1IE -0-- -000 -0-- -000 PIR1 — ADIF —
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PIC16F716 8.0 ENHANCED CAPTURE/ COMPARE/PWM MODULE Note: The Enhanced Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate a Pulse-Width Modulated signal of varying frequency and duty cycle.
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PIC16F716 8.1 Capture Mode 8.1.2 In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin CCP1. An event is defined as one of the following and is configured by the CCP1M<3:0> bits of the CCP1CON register: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge When a capture is made, the Interrupt Request Flag bit CCP1IF of the PIR1 register is set. The interrupt flag must be cleared in software.
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PIC16F716 TABLE 8-2: Name REGISTERS ASSOCIATED WITH CAPTURE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx xxxx xxxx CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx xxxx xxxx CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x PIE1 — ADIE — — — CCP1IE TMR2IE TMR1IE -0-- -0
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PIC16F716 8.2 Compare Mode 8.2.2 In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCP1 module may: • • • • • Toggle the CCP1 output. Set the CCP1 output. Clear the CCP1 output. Generate a Special Event Trigger. Generate a Software Interrupt. All Compare modes can generate an interrupt.
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PIC16F716 TABLE 8-3: Name REGISTERS ASSOCIATED WITH COMPARE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx xxxx xxxx CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx xxxx xxxx CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x PIE1 — ADIE — — — CCP1IE TMR2IE TMR1IE -0-- -0
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PIC16F716 8.3 PWM Mode The PWM mode generates a Pulse-Width Modulated signal on the CCP1 pin. The duty cycle, period and resolution are determined by the following registers: • • • • PR2 T2CON CCPR1L CCP1CON FIGURE 8-4: CCP PWM OUTPUT Period Pulse Width In Pulse-Width Modulation (PWM) mode, the CCP module produces up to a 10-bit resolution PWM output on the CCP1 pin. Since the CCP1 pin is multiplexed with the PORT data latch, the TRIS for that pin must be cleared to enable the CCP1 pin output driver.
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PIC16F716 8.3.1 PWM PERIOD The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 8-1. EQUATION 8-1: PWM PERIOD PWM Period = [ ( PR2 ) + 1 ] • 4 • T OSC • (TMR2 Prescale Value) When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The CCP1 pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) • The PWM duty cycle is latched from CCPR1L into CCPR1H.
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PIC16F716 8.3.3 PWM RESOLUTION EQUATION 8-4: The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 8-4.
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PIC16F716 8.3.4 OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 8.3.5 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. 8.3.6 8.3.
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PIC16F716 8.3.8 ENHANCED PWM AUTOSHUTDOWN MODE When a shutdown event occurs, two things happen: The ECCPASE bit is set to ‘1’. The ECCPASE will remain set until cleared in firmware or an auto-restart occurs (see Section 8.3.9 “Auto-Restart Mode”). The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state.
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PIC16F716 REGISTER 8-2: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 — ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs are in shutdown state 0 = ECC
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PIC16F716 FIGURE 8-6: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PRSEN = 0) Shutdown Event ECCPASE bit PWM Activity PWM Period ECCPASE Cleared by Shutdown Shutdown Firmware PWM Event Occurs Event Clears Resumes Start of PWM Period 8.3.9 AUTO-RESTART MODE The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PRSEN bit in the PWM1CON register.
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PIC16F716 8.3.10 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 8-8: In Half-Bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off.
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PIC16F716 REGISTER 8-3: PWM1CON: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = U
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PIC16F716 9.0 SPECIAL FEATURES OF THE CPU The PIC16F716 device has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power-saving operating modes and offer code protection. These are: • OSC Selection • Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) • Interrupts • Watchdog Timer (WDT) • Sleep • Code protection • ID locations • In-Circuit Serial Programming™ (ICSP™) 9.
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PIC16F716 REGISTER 9-1: — CONFIG: CONFIGURATION WORD REGISTER — CP(2) — — — — — bit 15 bit 8 BOREN(1) BORV — — PWRTE WDTE FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit P = Programmable’ U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘1’ bit 13 CP: Code Protection bit(2) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled
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PIC16F716 9.2 Oscillator Configurations 9.2.1 TABLE 9-1: Ranges Tested: OSCILLATOR TYPES The PIC16F716 can be operated in four different oscillator modes. The user can program two Configuration bits (FOSC1 and FOSC0) to select one of these four modes: • • • • LP – Low-power Crystal XT – Crystal/Resonator HS – High-speed Crystal/Resonator RC – Resistor/Capacitor 9.2.
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PIC16F716 9.2.3 RC OSCILLATOR For timing insensitive applications, the “RC” device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this, the oscillator frequency will vary from unit-to-unit due to normal process parameter variation.
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PIC16F716 9.5 Power-up Timer (PWRT) The Power-up Timer provides a fixed nominal time-out, on power-up only, from the POR. The Power-up Timer operates on an internal RC oscillator. The chip is kept in Reset as long as the PWRT is active. The PWRT’s time delay allows VDD to rise to an acceptable level. The power-up timer enable Configuration bit, PWRTE, is provided to enable/disable the PWRT. The power-up time delay will vary from chip-to-chip due to VDD, temperature and process variation.
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PIC16F716 FIGURE 9-5: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR WDT Module Sleep WDT Time-out Reset VDD rise detect Power-on Reset VDD Brown-out Reset S BOREN OST/PWRT OST Chip_Reset R 10-bit Ripple counter Q OSC1 (1) On-chip RC OSC PWRT 10-bit Ripple counter PWRTE See Table 9-3 for time-out situations. Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
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PIC16F716 FIGURE 9-7: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 1 VDD FIGURE 9-9: VDD VDD 33k MCP809 Q1 10k MCLR 40k EXTERNAL BROWN-OUT PROTECTION CIRCUIT 3 Vss VDD VDD RST PIC16F716 bypass capacitor MCLR PIC16F716 Note 1: This circuit will activate Reset when VDD goes below (Vz + 0.7V) where Vz = Zener voltage. 2: Internal Brown-out Reset circuitry should be disabled when using this circuit.
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PIC16F716 9.8 Time-out Sequence 9.9 On power-up, the time-out sequence is as follows: First PWRT time-out is invoked after the POR time delay has expired. Then OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figure 9-10, Figure 9-11, and Figure 9-12 depict time-out sequences on power-up.
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PIC16F716 TABLE 9-5: RESET CONDITION FOR SPECIAL REGISTERS Program Counter STATUS Register PCON Register Power-on Reset (BOREN = 0) 000h 0001 1xxx ---- --0x Power-on Reset (BOREN = 1) 000h 0001 1xxx ---- --01 MCLR Reset during normal operation 000h 000u uuuu ---- --uu MCLR Reset during Sleep 000h 0001 0uuu ---- --uu WDT Reset 000h 0000 1uuu ---- --uu PC + 1 uuu0 0uuu ---- --uu Condition WDT Wake-up Brown-out Reset Interrupt wake-up from Sleep 000h 0001 1uuu ---- --u0 PC + 1(1
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PIC16F716 TABLE 9-6: Register W INITIALIZATION CONDITIONS FOR ALL REGISTERS OF THE PIC16F716 Power-on Reset, Brown-out Reset MCLR Resets WDT Reset Wake-up via WDT or Interrupt xxxx xxxx uuuu uuuu uuuu uuuu INDF N/A N/A N/A TMR0 xxxx xxxx uuuu uuuu uuuu uuuu 0000h 0000h PC + 1(2) PCL (3) uuuq quuu(3) STATUS 0001 1xxx FSR xxxx xxxx uuuu uuuu uuuu uuuu PORTA(4), (5), (6) --xx 0000 --xx 0000 --uu uuuu PORTB(4), (5) xxxx xxxx uuuu uuuu uuuu uuuu PCLATH ---0 0000 ---0 0000 --
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PIC16F716 FIGURE 9-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 9-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 9-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET © 2007 Microchip Technology Inc.
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PIC16F716 9.10 Interrupts The peripheral interrupt flags are contained in the Special Function Registers, PIR1 and PIR2. The corresponding interrupt enable bits are contained in Special Function Registers, PIE1 and PIE2, and the peripheral interrupt enable bit is contained in Special Function Register, INTCON. The PIC16F716 devices have up to 7 sources of interrupt. The Interrupt Control Register (INTCON) records individual interrupt requests in flag bits.
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PIC16F716 9.10.1 9.11 INT INTERRUPT External interrupt on RB0/INT pin is edge triggered, either rising if bit INTEDG of the OPTION register is set, or falling if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF of the INTCON register is set. This interrupt can be disabled by clearing enable bit INTE of the INTCON register. Flag bit INTF must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt.
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PIC16F716 9.12 Watchdog Timer (WDT) WDT time-out period values may be found in the Electrical Specifications section under TWDT (parameter #31). Values for the WDT prescaler (actually a postscaler, but shared with the Timer0 prescaler) may be assigned using the OPTION register. The Watchdog Timer is a free running, on-chip, RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin.
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PIC16F716 9.13 Power-down Mode (Sleep) Power-Down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit of the STATUS register is cleared, the TO of the STATUS register bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low or high-impedance). The following peripheral interrupts can wake the device from Sleep: 1. 2. 3.
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PIC16F716 FIGURE 9-15: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF flag (INTCON Reg.) Interrupt Latency (Note 3) GIE bit (INTCON Reg.) Processor in Sleep INSTRUCTION FLOW PC PC Instruction fetched Inst(PC) = Sleep Instruction executed Inst(PC - 1) Note 9.
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PIC16F716 10.0 INSTRUCTION SET SUMMARY The PIC16F716 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction.
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PIC16F716 TABLE 10-2: PIC16F716 INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f – f, d f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Mov
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PIC16F716 10.2 Instruction Descriptions ADDLW Add literal and W Syntax: [ label ] ADDLW BCF k Operands: 0 ≤ k ≤ 255 Operation: (W) + k → (W) Status Affected: C, DC, Z Description: The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register.
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PIC16F716 BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT Operands: 0 ≤ f ≤ 127 0≤b<7 Operands: None Operation: Operation: skip if (f) = 1 Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is executed. If bit ‘b’ is ‘1’, then the next instruction is discarded and a NOP is executed instead, making this a two-cycle instruction.
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PIC16F716 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - 1 → (destination); skip if result = 0 Operation: (f) + 1 → (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
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PIC16F716 MOVWF Move W to f Syntax: [ label ] MOVF Move f Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 Operation: (W) → (f) Operation: (f) → (dest) Status Affected: None Status Affected: Z Description: Description: The contents of register f is moved to a destination dependent upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected.
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PIC16F716 RETFIE Return from Interrupt RETLW Return with literal in W Syntax: [ label ] Syntax: [ label ] RETFIE RETLW k Operands: None Operands: 0 ≤ k ≤ 255 Operation: TOS → PC, 1 → GIE Operation: k → (W); TOS → PC Status Affected: None Status Affected: None Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
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PIC16F716 RLF Rotate Left f through Carry SLEEP Enter Sleep mode Syntax: [ label ] Syntax: [ label ] SLEEP Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: None Operation: Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
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PIC16F716 SUBWF Subtract W from f XORLW Exclusive OR literal with W Syntax: [ label ] SUBWF f,d Syntax: [ label ] XORLW k Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (f) - (W) → (destination) Status Affected: C, DC, Z Description: SWAPF Operation: (W) .XOR. k → (W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register.
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PIC16F716 11.
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PIC16F716 11.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.
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PIC16F716 11.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
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PIC16F716 11.11 PICSTART Plus Development Programmer 11.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins.
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PIC16F716 12.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias......................................................................................................... .-55°C to +125°C Storage temperature ........................................................................................................................... -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ....................................... -0.3V to (VDD +0.
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PIC16F716 PIC16F716 VOLTAGE-FREQUENCY GRAPH, -40°C < TA < +85°C(1) FIGURE 12-1: 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. PIC16F716 VOLTAGE-FREQUENCY GRAPH, 85°C < TA < +125°C(1) FIGURE 12-2: 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
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PIC16F716 12.1 DC Characteristics: PIC16F716 (Industrial, Extended) DC CHARACTERISTICS Param No. Sym VDD Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Min Typ† Max Units 2.0 3.0 — — 5.5 5.5 V V — 1.
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PIC16F716 12.2 DC Characteristics: PIC16F716 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C DC CHARACTERISTICS Param No. Sym VDD Characteristic 2.0 — Max Units VDD Conditions 5.5 V — Supply Current D010 D011 D012 D013 IPD Typ† Supply Voltage D001 IDD Min — 14 17 μA 2.0 — 23 28 μA 3.0 — 45 63.7 μA 5.0 — 120 160 μA 2.0 — 180 250 μA 3.0 — 290 370 μA 5.0 — 220 300 μA 2.0 — 350 470 μA 3.
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PIC16F716 12.3 DC Characteristics: PIC16F716 (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C DC CHARACTERISTICS Param No. Sym VDD Characteristic Min 3.0 Conditions — 5.5 V — Supply Current D010E D011E D012E D013E IPD VDD Supply Voltage D001 IDD Typ† Max Units — 21 28 μA 3.0 — 38 63.7 μA 5.0 — 182 250 μA 3.0 — 293 370 μA 5.0 — 371 470 μA 3.0 — 668 780 μA 5.0 — 2.6 2.9 mA 4.5 — 3 3.3 mA 5.
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PIC16F716 12.4 DC Characteristics: PIC16F716 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Operating voltage VDD range as described in DC spec Section 12.1 “DC Characteristics: PIC16F716 (Industrial, Extended)” and Section 12.4 “DC Characteristics: PIC16F716 (Industrial, Extended)”. DC CHARACTERISTICS Param No.
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PIC16F716 12.5 12.5.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low © 2007 Microchip Technology Inc.
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PIC16F716 12.5.2 TIMING CONDITIONS The temperature and voltages specified in Table 12-1 apply to all timing specifications, unless otherwise noted. Figure 12-3 specifies the load conditions for the timing specifications.
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PIC16F716 TABLE 12-2: Param No. Sym EXTERNAL CLOCK TIMING REQUIREMENTS Characteristic Min Typ† Max Units Conditions Ext. Clock Input Frequency(1) DC — 4 MHz RC and XT Osc modes DC — 20 MHz HS Osc mode DC — 200 kHz LP Osc mode (1) Oscillator Frequency DC — 4 MHz RC Osc mode 0.
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PIC16F716 FIGURE 12-5: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note 1: Refer to Figure 12-3 for load conditions. TABLE 12-3: Param No.
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PIC16F716 FIGURE 12-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING(1) VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O Pins Note 1: Refer to Figure 12-3 for load conditions. FIGURE 12-7: BROWN-OUT RESET TIMING BVDD VDD TABLE 12-4: Param No.
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PIC16F716 TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS(1) FIGURE 12-8: T0CKI 41 40 42 T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note 1: Refer to Figure 12-3 for load conditions. TABLE 12-5: Param No. TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Sym Characteristic 40* Tt0H T0CKI High Pulse Width 41* Tt0L T0CKI Low Pulse Width 42* Tt0P T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler No Prescaler With Prescaler Typ† Max Units Conditions 0.5TCY + 20 10 0.
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PIC16F716 FIGURE 12-9: CAPTURE/COMPARE/PWM TIMINGS(1) CCP1 (Capture Mode) 50 51 52 CCP1 (Compare or PWM Mode) 53 Note 1: Refer to Figure 12-3 for load conditions. TABLE 12-6: CAPTURE/COMPARE/PWM REQUIREMENTS Param Sym No. 50* 51* TccL CCP1 input low time Characteristic Min — — ns 10 — — ns 0.
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PIC16F716 TABLE 12-7: A/D CONVERTER CHARACTERISTICS: PIC16F716 (INDUSTRIAL, EXTENDED) Param Sym No. Characteristic A00 VDD VDD Operation A01 NR A02 Resolution EABS Total Absolute error Min Typ† Max Units Conditions 2.5 — 5.5 V — — 8-bits bit — — <±1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A03 EIL Integral linearity error — — <±1 LSb VREF = VDD = 5.
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PIC16F716 FIGURE 12-10: A/D CONVERSION TIMING BSF ADCON0, GO 134 1 Tcy (TOSC/2)(1) 131 Q4 130 A/D CLK 132 7 A/D DATA 6 5 4 3 2 1 0 NEW_DATA OLD_DATA ADRES ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: TABLE 12-8: Param No. Sym 130 TAD If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
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PIC16F716 13.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range.
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PIC16F716 FIGURE 13-2: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) EC Mode 4.0 3.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 5.5V 5.0V 3.0 IDD (mA) 2.5 4.0V 2.0 3.0V 1.5 2.0V 1.0 0.5 0.0 1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz FOSC FIGURE 13-3: TYPICAL IDD vs. FOSC OVER VDD (HS MODE) Typical IDD vs. FOSC Over Vdd HS Mode 4.0 3.
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PIC16F716 FIGURE 13-4: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE) Maximum IDD vs. FOSC Over Vdd HS Mode 5.0 4.5 4.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 5.5V IDD (mA) 3.5 5.0V 3.0 4.5V 2.5 2.0 1.5 4.0V 3.5V 3.0V 1.0 0.5 0.0 4 MHz 10 MHz 16 MHz 20 MHz FOSC FIGURE 13-5: TYPICAL IDD vs.
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PIC16F716 FIGURE 13-6: MAXIMUM IDD vs. VDD OVER FOSC (XT MODE) XT Mode 1,400 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 1,200 IDD (μA) 1,000 800 4 MHz 600 400 1 MHz 200 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.0 5.5 VDD (V) FIGURE 13-7: TYPICAL IDD vs. VDD OVER FOSC (EXTRC MODE) EXTRC Mode 800 700 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 600 IDD (μA) 500 4 MHz 400 300 1 MHz 200 100 0 2.0 2.5 3.
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PIC16F716 FIGURE 13-8: MAXIMUM IDD vs. VDD (EXTRC MODE) EXTRC Mode 1,400 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 1,200 1,000 4 MHz IDD (μA) 800 600 1 MHz 400 200 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 4.5 5.0 5.5 VDD (V) FIGURE 13-9: IDD vs. VDD (LP MODE) 70 60 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) IDD (μA) 50 32 kHz Maximum 40 30 32 kHz Typical 20 10 0 2.0 2.5 3.0 3.5 4.0 5.
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PIC16F716 FIGURE 13-10: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Typical (Sleep Mode all Peripherals Disabled) 0.45 0.40 0.35 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) IPD (μA) 0.30 0.25 0.20 0.15 0.10 0.05 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 13-11: MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Maximum (Sleep Mode all Peripherals Disabled) 18.0 16.
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PIC16F716 FIGURE 13-12: BOR IPD vs. VDD OVER TEMPERATURE 160 140 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 120 IPD (μA) 100 80 Maximum 60 40 Typical 20 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 13-13: TYPICAL WDT IPD vs. VDD OVER TEMPERATURE Typical 3.0 2.5 Typical: Statistical StatisticalMean Mean @25°C @25°C Typical: Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) IPD (μA) 2.0 1.5 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.
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PIC16F716 FIGURE 13-14: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE Maximum 25.0 20.0 IPD (μA) Max. 125°C 15.0 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 10.0 Max. 85°C 5.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 13-15: WDT PERIOD vs. VDD OVER TEMPERATURE 30 28 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Max. (125°C) 26 Max. (85°C) 24 Time (ms) 22 20 Typical 18 16 14 Minimum 12 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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PIC16F716 FIGURE 13-16: WDT PERIOD vs. TEMPERATURE OVER VDD (5.0V) Vdd = 5V 30 28 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 26 Maximum 24 Time (ms) 22 20 Typical 18 16 Minimum 14 12 10 -40°C 25°C 85°C 125°C Temperature (°C) © 2007 Microchip Technology Inc.
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PIC16F716 FIGURE 13-17: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V) (VDD = 3V, -40×C TO 125×C) 0.8 0.7 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Max. 125°C 0.6 VOL (V) 0.5 Max. 85°C 0.4 Typical 25°C 0.3 0.2 Min. -40°C 0.1 0.0 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V) FIGURE 13-18: 0.
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PIC16F716 FIGURE 13-19: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V) 3.5 3.0 Max. -40°C Typ. 25°C 2.5 Min. 125°C VOH (V) 2.0 1.5 1.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 0.5 0.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 IOH (mA) FIGURE 13-20: (VDD = 5.0V) VOH vs. IOH OVER TEMPERATURE ( , ) 5.5 5.0 Max. -40°C Typ. 25°C VOH (V) 4.5 Min. 125°C 4.0 3.
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PIC16F716 FIGURE 13-21: TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE (TTL Input, -40×C TO 125×C) 1.7 1.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Max. -40°C VIN (V) 1.3 Typ. 25°C 1.1 Min. 125°C 0.9 0.7 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 13-22: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE (ST Input, -40×C TO 125×C) 4.0 VIH Max. 125°C 3.
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PIC16F716 FIGURE 13-23: T1OSC IPD vs. VDD OVER TEMPERATURE (32 kHz) 45.0 40.0 Typical: Statistical Mean @25°C Maximum: Mean Mean (Worst-case Temp) + 3σ Maximum: (-40×C + 3 to 125×C) (-40°C to 125°C) 35.0 Max. 125°C IPD (mA) 30.0 25.0 20.0 15.0 Max. 85°C 10.0 5.0 Typ. 25°C 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) ADC CLOCK PERIOD vs.
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PIC16F716 14.0 PACKAGING INFORMATION 14.1 Package Marking Information 18-Lead PDIP Example PIC16F716-04/P e3 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 18-Lead SOIC (7.50 mm) XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX 0610017 Example PIC16F716-20 /SO e3 0610017 YYWWNNN 20-Lead SSOP Example XXXXXXXXXXX XXXXXXXXXXX YYWWNNN Legend: XX...
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PIC16F716 14.2 Package Details The following sections give the technical details of the packages. 18-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A2 A L c A1 b1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 18 Pitch e Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .
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PIC16F716 18-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 3 b e α h h c φ A2 A A1 β L L1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 18 Pitch e Overall Height A – 1.27 BSC – Molded Package Thickness A2 2.05 – – Standoff § A1 0.10 – 0.30 Overall Width E Molded Package Width E1 7.
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PIC16F716 20-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 b e c A2 A φ A1 L1 Units Dimension Limits Number of Pins L MILLIMETERS MIN N NOM MAX 20 Pitch e Overall Height A – 0.65 BSC – 2.00 Molded Package Thickness A2 1.65 1.75 1.85 Standoff A1 0.05 – – Overall Width E 7.40 7.80 8.
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PIC16F716 APPENDIX A: REVISION HISTORY Revision A (June 2003) Original data sheet. However, the device described in this data sheet are upgrades to PIC16C716. Revision B (February 2007) Updated with current formats and added Characterization Data. Replaced Package Drawings. © 2007 Microchip Technology Inc. APPENDIX B: CONVERSION CONSIDERATIONS This is a Flash program memory version of the PIC16C716 device.
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PIC16F716 APPENDIX C: MIGRATION FROM BASE-LINE TO MID-RANGE DEVICES To convert code written for PIC16C5X to PIC16F716, the user should take the following steps: 1. This section discusses how to migrate from a baseline device (i.e., PIC16C5X) to a mid-range device (i.e., PIC16F716). 2. The following are the list of modifications over the PIC16C5X microcontroller family: 3. 1. 4. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. Instruction word length is increased to 14-bits.
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PIC16F716 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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PIC16F716 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
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PIC16F716 INDEX A C A/D C Compilers MPLAB C18................................................................ 88 MPLAB C30................................................................ 88 Capture Module. See Enhanced Capture/Compare/ PWM(ECCP) Capture/Compare/PWM (CCP) Associated registers w/ Capture................................. 49 Associated registers w/ Compare............................... 51 Associated registers w/ PWM..................................... 60 Capture Mode.......................
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PIC16F716 E Firmware Instructions.......................................................... 77 Fuses. See Configuration Bits XORWF ...................................................................... 85 Summary Table .......................................................... 78 INT Interrupt (RB0/INT). See Interrupt Sources INTCON Register............................................................ 9, 13 Internal Sampling Switch (RSS) IMPEDANCE ........................ 43 Internet Address ..............
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PIC16F716 PORTA Register ..................................................... 9, 19 TRISA Register ..................................................... 10, 19 PORTB Associated Registers .................................................. 25 PORTB Register ..................................................... 9, 21 RB Interrupt-on-Change.............................................. 73 RB Interrupt-on-Change Enable (RBIE Bit) ................ 73 RB0/INT Pin, External.........................................
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PIC16F716 Timing Diagrams and Specifications................................... 98 A/D Conversion ......................................................... 105 Brown-out Reset (BOR) ............................................ 101 Capture/Compare/PWM (CCP)................................. 103 CLKOUT and I/O....................................................... 100 External Clock ............................................................. 98 Oscillator Start-up Timer (OST) ................................
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PIC16F716 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device: PIC16F716(1), PIC16F716T(2); VDD range 2.0V to 5.5V Temperature Range: I E = -40°C to +85°C = -40°C to +125°C Package: SO P SS = = = Pattern: QTP, SQTP, Code or Special Requirements (blank otherwise) PIC16F716 - I/L 301 = Industrial temp.
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WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.