Datasheet

PIC16F716
DS41206A-page 34 Preliminary  2003 Microchip Technology Inc.
7.1 Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RB3/CCP1/P1A. An event is defined as:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the
interrupt request flag bit CCP1IF (PIR1<2>) is set. It
must be cleared in software. If another capture occurs
before the value in register CCPR1 is read, the old
captured value will be lost.
FIGURE 7-1: CAPTURE MODE
OPERATION BLOCK
DIAGRAM
7.1.1 CCP1 PIN CONFIGURATION
In Capture mode, the RB3/CCP1/P1A pin should be
configured as an input by setting the TRISB<3> bit.
7.1.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or
Synchronized Counter mode for the ECCP module to
use the capture feature. In Asynchronous Counter
mode, the capture operation may not work.
7.1.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
7.1.4 ECCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the ECCP module is
turned off, or the ECCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 7-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 7-1: CHANGING BETWEEN
CAPTURE PRESCALERS
7.2 Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RB3/CCP1/P1A pin is
either:
• Driven High
•Driven Low
• Toggle output (high-to-low or low-to-high)
• Remains Unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
Changing the ECCP mode to clear output on match
(CCP1M<3:0> = 1000) presets the CCP1 output latch
to the logic 1 level. Changing the ECCP mode to set
output on match (CCP1M<3:0> = 1001) presets the
CCP1 output latch to the logic 0 level.
Note: Always reset the ECCP module
(CCP1M3:CCP1M0 = ‘0000’) between
changing from one capture mode to
another. This is necessary to reset the
internal capture counter.
Note: If the RB3/CCP1/P1A is configured as an
output, a write to PORTB can cause a
capture condition.
CCPR1H CCPR1L
TMR1H TMR1L
Set flag bit CCP1IF
(PIR1<2>)
Capture
Enable
Q’s
CCP1CON<3:0>
RB3/CCP1/P1A
Prescaler
1, 4, 16
and
edge detect
Pin
CLRF CCP1CON ;Turn ECCP module off
MOVLW NEW_CAPT_PS ;Load the W reg with
;the new prescaler
;mode value and ECCP ON
MOVWF CCP1CON ;Load CCP1CON with this
;value