PIC16F716 Data Sheet 8-bit Flash-based Microcontroller with A/D Converter and Enhanced Capture/Compare/PWM 2003 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC16F716 8-bit Flash-based Microcontroller with A/D Controller and Enhanced Capture/Compare PWM Microcontroller Core Features: Low-Power Features: • High-performance RISC CPU • Only 35 single-word instructions to learn - All single-cycle instructions except for program branches which are two-cycle • Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle • Interrupt capability (up to 7 internal/external interrupt sources) • 8-level deep hardware stack • Direct, Indirect and Relative Addres
PIC16F716 Pin Diagrams 18-pin PDIP, SOIC 1 2 3 4 5 6 7 8 9 PIC16F716 RA2/AN2 RA3/AN3/VREF RA4/T0CKI MCLR/VPP VSS RB0/INT/ECCPAS2 RB1/T1OSO/T1CKI RB2/T1OSI RB3/CCP1/P1A 18 17 16 15 14 13 12 11 10 RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT VDD RB7/P1D RB6/P1C RB5/P1B RB4/ECCPAS0 20 19 18 17 16 15 14 13 12 11 RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT VDD VDD RB7/P1D RB6/P1C RB5/P1B RB4/ECCPAS0 20-pin SSOP DS41206A-page 2 1 2 3 4 5 6 7 8 9 10 PIC16F716 RA2/AN2 RA3/AN3/VREF RA4/T0CKI MCLR/VPP VSS VSS RB0/INT
PIC16F716 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Memory Organization ................................................................................................................................................................... 7 3.0 I/O Ports .......................................................................................
PIC16F716 NOTES: DS41206A-page 4 Preliminary 2003 Microchip Technology Inc.
PIC16F716 1.0 DEVICE OVERVIEW This document contains device specific information for the PIC16F716. Additional information may be found in the PICmicro® Mid-Range Reference Manual, (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site (www.microchip.com).
PIC16F716 TABLE 1-1: PIC16F716 PINOUT DESCRIPTION Name Function Input Type Output Type Description Master clear (Reset) input. This pin is an active low Reset to the device. MCLR/VPP MCLR VPP P — Programming voltage input OSC1/CLKIN OSC1 XTAL — Oscillator crystal input CLKIN CMOS — External clock source input CLKIN ST — RC Oscillator mode OSC2 XTAL — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode.
PIC16F716 2.0 MEMORY ORGANIZATION 2.2 There are two memory blocks in the PIC16F716 PICmicro® microcontroller device. Each block (program memory and data memory) has its own bus so that concurrent access can occur. The data memory is partitioned into multiple banks which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). Bits RP1 and RP0 of the Status register are the bank select bits.
PIC16F716 2.2.1 GENERAL PURPOSE REGISTER FILE FIGURE 2-2: The register file can be accessed either directly or indirectly through the File Select Register FSR (Section 2.5 “Indirect Addressing, INDF and FSR Registers”).
PIC16F716 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is give in Table 2-1. The Special Function Registers can be classified into two sets; core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section.
PIC16F716 TABLE 2-2: Address SPECIAL FUNCTION REGISTER SUMMARY BANK 1 Name 80h INDF(1) 81h OPTION_REG 82h PCL(1) 83h STATUS(1) 84h FSR(1) 85h TRISA 86h TRISB 87h-89h — 8Ah PCLATH(1,2) 8Bh INTCON(1) 8Ch PIE1 8Dh — 8Eh PCON 8Fh-91h 92h 9Fh Note 1: 2: 3: 4: 5: 6: 7: Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter's (PC) Least Sign
PIC16F716 2.2.2.1 Status Register The Status register, shown in Register 2-1, contains the arithmetic status of the ALU, the Reset status and the bank select bits for data memory. The Status register can be the destination for any instruction, as with any other register. If the Status register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
PIC16F716 2.2.2.2 OPTION_REG Register Note: The OPTION_REG register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 2-2: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer.
PIC16F716 2.2.2.3 INTCON Register Note: The INTCON Register is a readable and writable register which contains various enable and flag bits for the TMR0 register overflow, RB Port change and external RB0/INT pin interrupts. REGISTER 2-3: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16F716 2.2.2.4 PIE1 Register Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. This register contains the individual enable bits for the peripheral interrupts.
PIC16F716 2.2.2.5 PIR1 Register Note: This register contains the individual flag bits for the peripheral interrupts. REGISTER 2-5: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16F716 2.2.2.6 PCON Register Note: The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR) to an external MCLR Reset or WDT Reset. These devices contain an additional bit to differentiate a Brown-out Reset condition from a Power-on Reset condition. If the BOREN configuration bit is set, BOR is ‘1’ on Power-on Reset and reset to ‘0’ when a Brown-out condition occurs.
PIC16F716 2.3 FIGURE 2-3: PCL and PCLATH The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 13 bits wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called the PCH register. This register contains the PC<12:8> bits and is not directly readable or writable. All updates to the PCH register go through the PCLATH register. 2.3.
PIC16F716 2.5 EXAMPLE 2-2: Indirect Addressing, INDF and FSR Registers The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.
PIC16F716 3.0 I/O PORTS EXAMPLE 3-1: Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the PICmicro® Mid-Range Reference Manual, (DS33023). 3.1 PORTA and the TRISA Register PORTA is a 5-bit wide bidirectional port. The corresponding data direction register is TRISA.
PIC16F716 FIGURE 3-2: BLOCK DIAGRAM OF RA4/T0CKI PIN Data Latch DATA BUS Q D WR PORT CK RA4/T0CKI Q N TRIS Latch WR TRIS VSS Q D CK VSS Schmitt Trigger Input Buffer Q RD TRIS Q D ENEN RD PORT TMR0 Clock Input TABLE 3-1: PORTA FUNCTIONS Name RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI Bit# Buffer bit 0 bit 1 bit 2 bit 3 bit 4 TTL TTL TTL TTL ST Function Input/output or analog input Input/output or analog input Input/output or analog input Input/output or analog input or VREF
PIC16F716 3.2 PORTB and the TRISB Register PORTB is an 8-bit wide bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin).
PIC16F716 FIGURE 3-4: BLOCK DIAGRAM OF RB1/T1OSO/T1CKI PIN VDD T1OSCEN RBPU(1) weak P pull-up VDD DATA BUS Data Latch D WR PORTB CK RB1/T1OSO/T1CKI Q Q TRIS Latch D WR TRISB CK VSS Q Q RD TRISB T1OSCEN TTL Buffer Q D EN RD PORTB T1OSI (From RB2) TMR1 oscillator To Timer1 clock input ST Buffer Note FIGURE 3-5: 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
PIC16F716 FIGURE 3-6: BLOCK DIAGRAM OF RB3/CCP1/P1A PIN VDD RBPU(1) [PWMA(P1A) / CCP1 Compare] Output Enable [PWMA(P1A) / CCP1 Compare] Output weak P pull-up VDD 1 RB3/CCP1/P1A 0 PWMA(P1A) Auto-shutdown tri-state VSS Data Latch DATA BUS D WR PORTB CK Q Q TRIS Latch D WR TRISB CK Q Q RD TRIS TTL Buffer Q D EN RD PORTB Schmitt Trigger Buffer CCP - Capture input Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
PIC16F716 FIGURE 3-8: BLOCK DIAGRAM OF RB5/P1B PIN VDD RBPU(1) PWMB(P1B) Enable PWMB(P1B) Data out PWMB(P1B) Auto-shutdown tri-state Data Latch DATA BUS D Q WR PORTB weak P pull-up VDD 1 RB5/P1B 0 CK TRIS Latch D Q WR TRISB CK VSS TTL Buffer Q RD TRISB Q Latch D EN RD PORTB Q1 Set RBIF Q From other RB7:RB4 pins D RD PORTB Q3 EN Note FIGURE 3-9: 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
PIC16F716 FIGURE 3-10: BLOCK DIAGRAM OF RB7/P1D PIN VDD RBPU(1) PWMD(P1D) Enable PWMD(P1D) Data out PWMD(P1D) Auto-shutdown tri-state Data Latch DATA BUS D Q WR PORTB weak P pull-up VDD 1 RB7/P1D 0 CK TRIS Latch D Q WR TRISB CK VSS Q ST Buffer RD TRISB Q Latch D EN RD PORTB TTL Buffer Q1 Set RBIF Q From other RB7:RB4 pins D EN Note RD PORTB Q3 ICSPD - In circuit serial programming data input TABLE 3-3: Name 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the R
PIC16F716 TABLE 3-4: Address 06h SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name PORTB 86h TRISB 81h OPTION_REG Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 PORTB Data Direction Register RBPU INTEDG T0CS Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
PIC16F716 4.0 TIMER0 MODULE 4.2 An 8-bit counter is available as a prescaler for the Timer0 module or as a postscaler for the Watchdog Timer, respectively (Figure 4-2). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet.
PIC16F716 4.2.1 SWITCHING PRESCALER ASSIGNMENT 4.3 The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from Sleep since the timer is shut off during Sleep.
PIC16F716 5.0 TIMER1 MODULE 5.1 The Timer1 module timer/counter has the following features: • 16-bit timer/counter (Two 8-bit registers; TMR1H and TMR1L) • Readable and writable (Both registers) • Internal or external clock select • Interrupt on overflow from FFFFh to 0000h • Reset from ECCP module trigger Timer1 can operate in one of these modes: • As a timer • As a synchronous counter • As an asynchronous counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>).
PIC16F716 FIGURE 5-1: TIMER1 BLOCK DIAGRAM Set flag bit TMR1IF on Overflow Synchronized clock input 0 TMR1 TMR1L TMR1H 1 TMR1ON on/off T1SYNC T1OSC RB1/T1OSO/T1CKI 1 T1OSCEN FOSC/4 Enable Internal Oscillator(1) Clock RB2/T1OSI Note 1: 5.2 Synchronize Prescaler 1, 2, 4, 8 det 0 2 T1CKPS1:T1CKPS0 TMR1CS Sleep input When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. which is latched in interrupt flag bit TMR1IF (PIR1<0>).
PIC16F716 6.0 TIMER2 MODULE Figure 6-1 is a simplified block diagram of the Timer2 module. The Timer2 module timer has the following features: • • • • • • Additional information on timer modules is available in the PICmicro® Mid-Range Reference Manual, (DS33023).
PIC16F716 6.1 Timer2 Operation 6.2 Timer2 can be used as the PWM time base for PWM mode of the ECCP module. Timer2 Interrupt The Timer2 module has an 8-bit Period register (PR2). Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset.
PIC16F716 7.0 ENHANCED CAPTURE/ COMPARE/PWM (ECCP) MODULE The CCP1CON register controls ECCP operation. All the CCP1CON bits are readable and writable. The ECCP (Enhanced Capture/Compare/PWM) module contains a 16-bit register, which can operate as: Additional information on the ECCP module is available in the PICmicro® Mid-Range Reference Manual, (DS33023).
PIC16F716 7.1 7.1.4 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RB3/CCP1/P1A. An event is defined as: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set. It must be cleared in software.
PIC16F716 7.2.1 CCP1 PIN CONFIGURATION The user must configure the RB3/CCP1/P1A pin as the CCP1 output by clearing the TRISB<3> bit. Note: 7.2.2 Note: Clearing the CCP1CON register will force the RB3/CCP1/P1A compare output latch to the default low level. This is not the PORTB I/O data latch. The special event trigger from the ECCP module will not set interrupt flag bit TMR1IF (PIR1<0>).
PIC16F716 7.3 PWM Mode In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTB data latch, the TRISB<3> bit must be cleared to make the CCP1 pin an output. Note: A PWM output (Figure 7-4) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).
PIC16F716 7.3.2 PWM DUTY CYCLE EQUATION 7-3: The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time: log Max resolution = Note: If the PWM duty cycle value is longer than the PWM period the CCP1 pin will not be cleared.
PIC16F716 7.4 7.4.1 ENHANCED PWM MODE PWM OUTPUT CONFIGURATIONS The P1M1:P1M0 bits in the CCP1CON register allows one of four configurations: The Enhanced PWM mode provides additional PWM output options for a broader range of control applications. The module is an upwardly compatible version of the standard CCP module and offers up to four outputs, designated P1A through P1D. Users are also able to select the polarity of the signal (either active-high or active-low).
PIC16F716 FIGURE 7-6: PWM OUTPUT RELATIONSHIPS (P1A, P1B, P1C, P1D ACTIVE-HIGH STATE) 0 00 PR2+1 Duty Cycle SIGNAL CCP1CON <7:6> Period (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active 01 P1B Inactive (Full-Bridge, Forward) P1C Inactive P1D Modulated P1A Inactive 11 P1B Modulated (Full-Bridge, Reverse) P1C Active P1D Inactive FIGURE 7-7: PWM OUTPUT RELATIONSHIPS (P1A, P1B, P1C, P1D ACTIVE-LOW STATE) 0 00 (Single Output) PR2+1
PIC16F716 FIGURE 7-8: PWM OUTPUT RELATIONSHIPS (P1A, P1C ACTIVE-HIGH. P1B, P1D ACTIVE-LOW) 0 CCP1CON <7:6> 00 (Single Output) PR2+1 Duty Cycle SIGNAL Period P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive DS41206A-page 40 Preliminary 2003 Microchip Technology Inc.
PIC16F716 FIGURE 7-9: PWM OUTPUT RELATIONSHIPS (P1A, P1C ACTIVE-LOW.
PIC16F716 7.4.2 HALF-BRIDGE MODE In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the RB3/CCP1/P1A pin, while the complementary PWM output signal is output on the RB5/P1B pin (Figure 7-12). This mode can be used for half-bridge applications, as shown in Figure 7-11 or for full-bridge applications, where four power switches are being modulated with two PWM signals.
PIC16F716 7.4.3 FULL-BRIDGE MODE P1A, P1B, P1C and P1D outputs are multiplexed with the PORTB<3> and PORTB<5:7> data latches. The TRISB<3> and TRISB<5:7> bits must be cleared to make the P1A, P1B, P1C, and P1D pins output. In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin RB3/CCP1/P1A is continuously active, and pin RB7/P1D is modulated. In the Reverse mode, RB6/P1C pin is continuously active, and RB5/P1B pin is modulated.
PIC16F716 Figure 7-14 shows an example where the PWM direction changes from forward to reverse, at a near 100% duty cycle. At time t1, the output P1A and P1D become inactive, while output P1C becomes active. In this example, since the turn-off time of the power devices is longer than the turn-on time, a shoot-through current may flow through power devices QC and QD (see Figure 7-12) for the duration of ‘t’.
PIC16F716 7.4.4 PROGRAMMABLE DEAD-BAND DELAY 7.4.5 In half-bridge applications where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off.
PIC16F716 REGISTER 7-2: PWM1CON: PWM CONFIGURATION REGISTER (ADDRESS: 18h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 bit 7 bit 0 bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically. 0 = Upon auto-shutdown, ECCPASE must be cleared in firmware to restart the PWM.
PIC16F716 7.4.5.1 Auto-Shutdown and Automatic Restart 7.4.6 The auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. This is enabled by setting the PRSEN bit of the PWM1CON register (PWM1CON<7>). In Shutdown mode with PRSEN = 1 (PWM1CON <7>) (Figure 7-15), the ECCPASE bit will remain set for as long as the cause of the shutdown continues. When the shutdown condition clears, the ECCPASE bit is cleared.
PIC16F716 7.4.7 SETUP FOR PWM OPERATION 8. Configure and start TMR2: The following steps should be taken when configuring the ECCP module for PWM operation: • Clear the TMR2 interrupt flag bit by clearing the TMR2IF bit (PIR1<1>). 1. • Set the TMR2 prescale value by loading the T2CKPSx bits (T2CON<1:0>). 2. 3. Configure the PWM pins P1A and P1B (and P1C and P1D, if used) as inputs by setting the corresponding TRISB bits. Set the PWM period by loading the PR2 register.
PIC16F716 8.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE Additional information on the A/D module is available in the PICmicro® Mid-Range Reference Manual, (DS33023). The Analog-to-Digital (A/D) Converter module has four inputs. The A/D module has three registers. These registers are: The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number (refer to Application Note AN546 for use of A/D Converter).
PIC16F716 REGISTER 8-2: ADCON1 REGISTER (ADDRESS: 9Fh) U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7-3 Unimplemented: Read as '0' bit 2-0 PCFG2:PCFG0: A/D Port Configuration Control bits AN3 RA3 AN2 RA2 AN2 RA1 AN0 RA0 0x0 A A A A VDD 0x1 VREF A A A RA3 PCFG2:PCFG0 VREF 100 A D A A VDD 101 VREF D A A RA3 D D D D VDD 11x Legend: A = Analog input, D = Digital I/O Legend: R = Readable bit W = Writable bit U = Uni
PIC16F716 FIGURE 8-1: A/D BLOCK DIAGRAM CHS2:CHS0 VIN 011 (Input voltage) RA3/AN3/VREF 010 RA2/AN2 A/D Converter 001 RA1/AN1 000 VDD RA0/AN0 000 or 010 or 100 or 110 or 111 VREF (Reference voltage) 001 or 011 or 101 PCFG2:PCFG0 8.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 8-2.
PIC16F716 8.2 Selecting the A/D Conversion Clock 8.3 The A/D conversion time per bit is defined as TAD. The A/D conversion requires 9.5 TAD per 8-bit conversion. The source of the A/D conversion clock is software selectable. The four possible options for TAD are: • • • • 2 TOSC 8 TOSC 32 TOSC Internal RC oscillator The ADCON1 and TRISA registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input).
PIC16F716 8.4 Note: 8.5 A/D Conversions The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. Use of the ECCP Trigger An A/D conversion can be started by the “special event trigger” of the ECCP module. This requires that the CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be programmed as ‘1011’ and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D conversion, and the Timer1 counter will be reset to zero.
PIC16F716 NOTES: DS41206A-page 54 Preliminary 2003 Microchip Technology Inc.
PIC16F716 9.0 SPECIAL FEATURES OF THE CPU The PIC16F716 device has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: • OSC Selection • Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) • Interrupts • Watchdog Timer (WDT) • Sleep • Code protection • ID locations • In-Circuit Serial Programming™ (ICSP™) 9.
PIC16F716 REGISTER 9-1: CP — CONFIGURATION WORD — — — — BORV BOREN — — PWRTE WDTE FOSC1 FOSC0 bit 13 bit 0 bit 13 CP: Flash Program Memory Code Protection bit 1 = Code protection off 0 = All program memory code protected bit 12-8 Unimplemented: Read as ‘1’ bit 7 BORV: Brown-out Reset Voltage bit 1 = VBOR set to 4.0V 0 = VBOR set to 2.
PIC16F716 9.2 TABLE 9-1: Oscillator Configurations 9.2.1 Ranges Tested: OSCILLATOR TYPES The PIC16F716 can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: • • • • LP - Low-power Crystal XT - Crystal/Resonator HS - High-speed Crystal/Resonator RC - Resistor/Capacitor 9.2.
PIC16F716 9.2.3 RC OSCILLATOR For timing insensitive applications, the “RC” device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation.
PIC16F716 9.5 Power-up Timer (PWRT) 9.7 The Power-up Timer provides a fixed nominal time-out, on power-up only, from the POR. The Power-up Timer operates on an internal RC oscillator. The chip is kept in Reset as long as the PWRT is active. The PWRT’s time delay allows VDD to rise to an acceptable level. The power-up timer enable configuration bit, PWRTE, is provided to enable/disable the PWRT. The power-up time delay will vary from chip-to-chip due to VDD, temperature and process variation.
PIC16F716 FIGURE 9-5: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR WDT Module Sleep WDT Time-out Reset VDD rise detect Power-on Reset VDD Brown-out Reset S BOREN OST/PWRT OST Chip_Reset R 10-bit Ripple counter Q OSC1 (1) On-chip RC OSC PWRT 10-bit Ripple counter PWRTE See Table 9-3 for time-out situations. Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
PIC16F716 FIGURE 9-7: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 1 VDD FIGURE 9-9: VDD VDD 33k MCP809 Q1 10k EXTERNAL BROWN-OUT PROTECTION CIRCUIT 3 Vss MCLR bypass capacitor VDD VDD 40k RST PIC16F716 MCLR PIC16F716 Note 1: This circuit will activate Reset when VDD goes below (Vz + 0.7V) where Vz = Zener voltage. 2: Internal Brown-out Reset circuitry should be disabled when using this circuit.
PIC16F716 9.8 Time-out Sequence 9.9 On power-up, the time-out sequence is as follows: First PWRT time-out is invoked after the POR time delay has expired. Then OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figure 9-10, Figure 9-11, and Figure 9-12 depict time-out sequences on power-up.
PIC16F716 TABLE 9-5: RESET CONDITION FOR SPECIAL REGISTERS Program Counter Status Register PCON Register Power-on Reset (BOREN = 0) 000h 0001 1xxx ---- --0x Power-on Reset (BOREN = 1) 000h 0001 1xxx ---- --01 MCLR Reset during normal operation 000h 000u uuuu ---- --uu MCLR Reset during Sleep 000h 0001 0uuu ---- --uu WDT Reset 000h 0000 1uuu ---- --uu PC + 1 uuu0 0uuu ---- --uu Condition WDT Wake-up Brown-out Reset Interrupt wake-up from Sleep 000h 0001 1uuu ---- --u0 PC + 1(1
PIC16F716 TABLE 9-6: Register W INITIALIZATION CONDITIONS FOR ALL REGISTERS OF THE PIC16F716 Power-on Reset, Brown-out Reset MCLR Resets WDT Reset Wake-up via WDT or Interrupt xxxx xxxx uuuu uuuu uuuu uuuu INDF N/A N/A N/A TMR0 xxxx xxxx uuuu uuuu uuuu uuuu 0000h 0000h PC + 1(2) PCL STATUS 0001 1xxx 000q quuu (3) uuuq quuu(3) FSR xxxx xxxx uuuu uuuu uuuu uuuu PORTA(4), (5), (6) --xx 0000 --xx 0000 --uu uuuu PORTB(4), (5) xxxx xxxx uuuu uuuu uuuu uuuu PCLATH ---0 0000 ---
PIC16F716 FIGURE 9-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 9-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 9-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 2003 Microchip Technology Inc.
PIC16F716 9.10 Interrupts The peripheral interrupt flags are contained in the special function registers, PIR1 and PIR2. The corresponding interrupt enable bits are contained in special function registers, PIE1 and PIE2, and the peripheral interrupt enable bit is contained in special function register, INTCON. The PIC16F716 devices have up to 7 sources of interrupt. The Interrupt Control Register (INTCON) records individual interrupt requests in flag bits.
PIC16F716 9.10.1 INT INTERRUPT 9.11 External interrupt on RB0/INT pin is edge triggered, either rising if bit INTEDG (OPTION_REG<6>) is set, or falling if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the interrupt service routine before re-enabling this interrupt.
PIC16F716 9.12 Watchdog Timer (WDT) The Watchdog Timer is a free running, on-chip, RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device have been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device Reset (Watchdog Timer Reset).
PIC16F716 9.13 Power-down Mode (Sleep) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low or high-impedance). The following peripheral interrupts can wake the device from Sleep: 1. 2. 3. TMR1 interrupt.
PIC16F716 FIGURE 9-16: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF flag (INTCON<1>) Interrupt Latency (Note 3) GIE bit (INTCON<7>) Processor in Sleep INSTRUCTION FLOW PC PC Instruction fetched Inst(PC) = Sleep Instruction executed Inst(PC - 1) Note 9.
PIC16F716 10.0 INSTRUCTION SET SUMMARY Each PIC16F716 instruction is a 14-bit word divided into an opcode which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16F716 instruction set summary in Table 10-2 lists byte-oriented, bitoriented, and literal and control operations. Table 10-1 shows the opcode field descriptions.
PIC16F716 TABLE 10-2: PIC16F716 INSTRUCTION SET 14-Bit Opcode Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f — f, d f, d f, d f, d f, d f, d f, d f — f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move
PIC16F716 10.1 Instruction Descriptions ADDLW Add Literal and W Syntax: [ label ] ADDLW Operands: ANDLW AND Literal with W Syntax: [ label ] ANDLW 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255 Operation: (W) + k → (W) Operation: (W) .AND. (k) → (W) Status Affected: C, DC, Z Status Affected: Z Encoding: 11 Encoding: 11 Description: The contents of the W register are added to the eight bit literal ‘k’ and the result is placed in the W register.
PIC16F716 BCF Bit Clear f BTFSC Bit Test f, Skip if Clear Syntax: [ label ] BCF Syntax: [ label ] BTFSC f,b Operands: 0 ≤ f ≤ 127 0≤b≤7 Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: 0 → (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Encoding: 01 Description: Bit ‘b’ in register ‘f’ is cleared.
PIC16F716 BTFSS Bit Test f, Skip if Set CALL Call Subroutine Syntax: [ label ] BTFSS f,b Syntax: [ label ] CALL k Operands: 0 ≤ f ≤ 127 0≤b<7 Operands: 0 ≤ k ≤ 2047 Operation: Operation: skip if (f) = 1 Status Affected: None (PC)+ 1→ TOS, k → PC<10:0>, (PCLATH<4:3>) → PC<12:11> Encoding: 01 Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘1’ then the next instruction is skipped.
PIC16F716 CLRW Clear W COMF Complement f Syntax: [ label ] CLRW Syntax: [ label ] COMF Operands: None Operands: Operation: 00h → (W) 1→Z 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) → (dest) Status Affected: Z Status Affected: Z Encoding: 00 Encoding: 00 Description: W register is cleared. Zero bit (Z) is set. Description: Words: 1 Cycles: 1 The contents of register ‘f’ are complemented. If ‘d’ is 0 the result is stored in W. If ‘d’ is 1 the result is stored back in register ‘f’.
PIC16F716 DECFSZ Decrement f, Skip if 0 GOTO Unconditional Branch Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ k ≤ 2047 Operation: (f) - 1 → (dest); 0 Operation: k → PC<10:0> PCLATH<4:3> → PC<12:11> Status Affected: None Status Affected: None Encoding: Encoding: 10 00 Description: The contents of register ‘f’ are decremented. If ‘d’ is 0 the result is placed in the W register. If ‘d’ is 1 the result is placed back in register ‘f’.
PIC16F716 INCF Increment f INCFSZ Increment f, Skip if 0 Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) + 1 → (dest) Operation: (f) + 1 → (dest), skip if result = 0 Status Affected: Z Status Affected: None Encoding: 00 Encoding: 00 Description: The contents of register ‘f’ are incremented. If ‘d’ is 0 the result is placed in the W register. If ‘d’ is 1 the result is placed back in register ‘f’.
PIC16F716 IORLW Inclusive OR Literal with W MOVLW Move Literal to W Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255 Operation: (W) .OR. k → (W) Operation: k → (W) Status Affected: Z Status Affected: None Encoding: 11 Encoding: 11 Description: The contents of the W register is OR’ed with the eight bit literal ‘k’. The result is placed in the W register. Description: The eight bit literal ‘k’ is loaded into W register.
PIC16F716 MOVWF Move W to f OPTION Load Option Register Syntax: [ label ] Syntax: [ label ] 0 ≤ f ≤ 127 Operands: None Operands: Operation: (W) → (f) Operation: (W) → OPTION Status Affected: None Status Affected: None Encoding: 00 Encoding: 00 Description: The contents of the W register are loaded in the OPTION register. This instruction is supported for code compatibility with PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it.
PIC16F716 RETLW Return with Literal in W RLF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: Operation: k → (W); TOS → PC 0 ≤ f ≤ 127 d ∈ [0,1] Operation: See description below Status Affected: None Status Affected: C Encoding: 11 Encoding: 00 Description: The W register is loaded with the eight bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction.
PIC16F716 RRF Rotate Right f through Carry SUBLW Subtract W from Literal Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: k - (W) → (W) Operation: See description below C, DC, Z Status Affected: C Status Affected: Encoding: 00 Encoding: 11 Description: The contents of register ‘f’ are rotated one bit to the right through the Carry Flag. If ‘d’ is 0 the result is placed in the W register.
PIC16F716 SUBWF Subtract W from f SWAPF Swap Nibbles in f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - (W) → (dest) Operation: Status Affected: C, DC, Z (f<3:0>) → (dest<7:4>), (f<7:4>) → (dest<3:0>) Status Affected: None Encoding: 00 Encoding: 00 Description: Subtract (2’s complement method) W register from register ‘f’. If ‘d’ is 0 the result is stored in the W register.
PIC16F716 XORLW Exclusive OR Literal with W XORWF Exclusive OR W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) .XOR. (f) → (dest) Status Affected: Z Encoding: 00 Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is 0 the result is stored in the W register. If ‘d’ is 1 the result is stored back in register ‘f’. Words: 1 Cycles: 1 Example XORWF XORLW k Operation: (W) .XOR.
PIC16F716 11.0 DEVELOPMENT SUPPORT 11.
PIC16F716 11.3 MPLAB C17 and MPLAB C18 C Compilers 11.6 The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 11.
PIC16F716 11.9 MPLAB ICE 2000 High Performance Universal In-Circuit Emulator 11.11 MPLAB ICD 2 In-Circuit Debugger The MPLAB ICE 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers.
PIC16F716 11.14 PICDEM 1 PICmicro Demonstration Board 11.17 PICDEM 3 PIC16C92X Demonstration Board The PICDEM 1 demonstration board demonstrates the capabilities of the PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs.
PIC16F716 11.20 PICDEM 18R PIC18C601/801 Demonstration Board 11.23 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM 18R demonstration board serves to assist development of the PIC18C601/801 family of Microchip microcontrollers. It provides hardware implementation of both 8-bit Multiplexed/De-multiplexed and 16-bit memory modes. The board includes 2 Mb external Flash memory and 128 Kb SRAM memory, as well as serial EEPROM, allowing access to the wide range of memory types supported by the PIC18C601/801.
PIC16F716 NOTES: DS41206A-page 90 Preliminary 2003 Microchip Technology Inc.
PIC16F716 12.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias......................................................................................................... .-55°C to +125°C Storage temperature ........................................................................................................................... -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ....................................... -0.3V to (VDD +0.
PIC16F716 PIC16F716 VOLTAGE-FREQUENCY GRAPH, -40°C < TA < +85°C(1) FIGURE 12-1: 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. PIC16F716 VOLTAGE-FREQUENCY GRAPH, 85°C < TA < +125°C(1) FIGURE 12-2: 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
PIC16F716 12.1 DC Characteristics: PIC16F716 (Industrial, Extended) DC CHARACTERISTICS Param No. Sym VDD Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Min Typ† Max Units Conditions 2.0 3.0 — — 5.5 5.5 V V — 1.5* — V — Vss — V 0.05 TBD — — — — 3.65 4.0 4.35 V BOREN bit set, BOR bit = ‘1’ TBD 2.
PIC16F716 12.2 DC Characteristics: PIC16F716 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C DC CHARACTERISTICS Para m No. Sym VDD Characteristic 2.0 — — — Max Units VDD Conditions 5.5 V — 0.1 0.8 µA 2.0 0.1 0.85 µA 3.0 — 0.2 2.7 µA 5.0 — 1 2.0 µA 2.0 — 2 3.5 µA 3.0 — 9 13.5 µA 5.0 — TBD TBD µA 3.0 — 40 TBD µA 4.5 — 45 TBD µA 5.0 — 1.8 TBD µA 2.0 — 2.6 TBD µA 3.0 — 3.
PIC16F716 12.3 DC Characteristics: PIC16F716 (Extended) DC CHARACTERISTICS Param No. Sym VDD Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Characteristic Typ† Max Units VDD Conditions Supply Voltage D001 IPD Min 3.0 — 5.5 V — — 0.1 TBD µA 3.0 — 0.2 TBD µA 5.0 — 2 TBD µA 3.0 9 TBD µA 5.0 TBD TBD µA 3.
PIC16F716 12.4 DC Characteristics: PIC16F716 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Operating voltage VDD range as described in DC spec Section 12.1 “DC Characteristics: PIC16F716 (Industrial, Extended)” and Section 12.4 “DC Characteristics: PIC16F716 (Industrial, Extended)”. DC CHARACTERISTICS Param No.
PIC16F716 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Operating voltage VDD range as described in DC spec Section 12.1 “DC Characteristics: PIC16F716 (Industrial, Extended)” and Section 12.4 “DC Characteristics: PIC16F716 (Industrial, Extended)”. DC CHARACTERISTICS Param No. Sym Note Min Typ† Max Units Conditions — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1.
PIC16F716 12.5.2 TIMING CONDITIONS The temperature and voltages specified in Table 12-1 apply to all timing specifications, unless otherwise noted. Figure 12-3 specifies the load conditions for the timing specifications.
PIC16F716 TABLE 12-2: Param No. Sym EXTERNAL CLOCK TIMING REQUIREMENTS Characteristic Min Typ† Max Units Conditions Ext. Clock Input Frequency(1) DC — 4 MHz RC and XT Osc modes DC — 20 MHz HS Osc mode DC — 200 kHz LP Osc mode (1) Oscillator Frequency DC — 4 MHz RC Osc mode 0.
PIC16F716 FIGURE 12-5: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note 1: Refer to Figure 12-3 for load conditions. TABLE 12-3: Param No.
PIC16F716 FIGURE 12-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING(1) VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O Pins Note 1: Refer to Figure 12-3 for load conditions. FIGURE 12-7: BROWN-OUT RESET TIMING BVDD VDD TABLE 12-4: Param No.
PIC16F716 TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS(1) FIGURE 12-8: T0CKI 41 40 42 T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note 1: Refer to Figure 12-3 for load conditions. TABLE 12-5: Param No.
PIC16F716 FIGURE 12-9: CAPTURE/COMPARE/PWM TIMINGS(1) CCP1 (Capture Mode) 50 51 52 CCP1 (Compare or PWM Mode) 53 Note 1: Refer to Figure 12-3 for load conditions. TABLE 12-6: CAPTURE/COMPARE/PWM REQUIREMENTS Param Sym No. 50* 51* TccL CCP1 input low time Characteristic Min — — ns 10 — — ns 0.
PIC16F716 TABLE 12-7: Para m No. A/D CONVERTER CHARACTERISTICS: PIC16F716 (INDUSTRIAL, EXTENDED) Sym Characteristic A00 VDD VDD Operation A01 NR A02 Resolution EABS Total Absolute error Min Typ† Max Units Conditions 2.5 — 5.5 V — — 8-bits bit — — <±1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A03 EIL Integral linearity error — — <±1 LSb VREF = VDD = 5.
PIC16F716 FIGURE 12-10: A/D CONVERSION TIMING BSF ADCON0, GO 134 1 Tcy (TOSC/2)(1) 131 Q4 130 A/D CLK 132 7 A/D DATA 6 5 4 3 2 1 0 NEW_DATA OLD_DATA ADRES ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: TABLE 12-8: Param No. Sym 130 TAD If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
PIC16F716 NOTES: DS41206A-page 106 Preliminary 2003 Microchip Technology Inc.
PIC16F716 13.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices will operate properly only within the specified range.
PIC16F716 NOTES: DS41206A-page 108 Preliminary 2003 Microchip Technology Inc.
PIC16F716 14.0 PACKAGING INFORMATION 14.1 Package Marking Information 18-Lead PDIP Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 18-Lead SOIC PIC16F716-04/P 0023CBA Example XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 20-Lead SSOP PIC16F716 -20/SO 0018CDK Example PIC16F716 -20I/SS025 XXXXXXXXXXX XXXXXXXXXXX YYWWNNN Legend: XX...
PIC16F716 18-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n α 1 E A2 A L c A1 B1 β p B eB Units Dimension Limits n p MIN INCHES* NOM 18 .100 .155 .130 MAX MILLIMETERS NOM 18 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 22.61 22.80 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .
PIC16F716 18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) E p E1 D 2 B n 1 h α 45° c A2 A φ β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom A A2 A1 E E1 D h L φ c B α β MIN .093 .088 .004 .394 .291 .446 .010 .016 0 .009 .014 0 0 A1 INCHES* NOM 18 .050 .099 .091 .
PIC16F716 20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP) E E1 p D B 2 1 n α c A2 A φ L A1 β Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top Mold Draft Angle Bottom A A2 A1 E E1 D L c φ B α β MIN .068 .064 .002 .299 .201 .278 .022 .004 0 .010 0 0 INCHES* NOM 20 .026 .073 .068 .006 .309 .207 .284 .030 .
PIC16F716 APPENDIX A: REVISION HISTORY APPENDIX B: Revision A (June 2003) Original data sheet. However, the device described in this data sheet are upgrades to PIC16C716. 2003 Microchip Technology Inc. CONVERSION CONSIDERATIONS This is a Flash program memory version of the PIC16C716 device. Refer to the migration document, DS40059, for more information about differences between the PIC16F716 and PIC16C716.
PIC16F716 APPENDIX C: MIGRATION FROM BASE-LINE TO MID-RANGE DEVICES To convert code written for PIC16C5X to PIC16F716, the user should take the following steps: 1. This section discusses how to migrate from a baseline device (i.e., PIC16C5X) to a mid-range device (i.e., PIC16F716). 2. The following are the list of modifications over the PIC16C5X microcontroller family: 3. 1. 4. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. Instruction word length is increased to 14-bits.
PIC16F716 ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape® or Microsoft® Internet Explorer. Files are also available for FTP download from our FTP site.
PIC16F716 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC16F716 INDEX A A/D ...................................................................................... 49 A/D Converter Enable (ADIE Bit) ................................ 14 A/D Converter Flag (ADIF Bit) .............................. 15, 50 A/D Converter Interrupt, Configuring .......................... 50 ADCON0 Register................................................... 9, 49 ADCON1 Register................................................. 10, 50 ADRES Register .....................................
PIC16F716 PICDEM 4 ................................................................... 88 PICDEM LIN PIC16C43X ........................................... 89 PICDEM USB PIC16C7X5.......................................... 89 PICDEM.net Internet/Ethernet .................................... 88 Development Support ......................................................... 85 Direct Addressing................................................................ 18 E ECCP Auto-Shutdown ...............................
PIC16F716 MPLAB Integrated Development Environment Software .... 85 MPLINK Object Linker/MPLIB Object Librarian .................. 86 N NOP Instruction................................................................... 80 O OPTION Instruction............................................................. 80 OPTION_REG Register ................................................ 10, 12 INTEDG Bit ................................................................. 12 PS2:PS0 Bits ..................................
PIC16F716 R RA3:RA0 ............................................................................. 19 RA4/T0CKI Pin.................................................................... 20 RAM. See Data Memory. RB0 Pin ............................................................................... 21 Register File .......................................................................... 8 Register File Map .................................................................. 8 Registers A/D ADCON0 ..............
PIC16F716 Reset......................................................................... 101 Timer0 and Timer1.................................................... 102 Watchdog Timer (WDT) ............................................ 101 TRIS Instruction .................................................................. 83 W W Register .......................................................................... 66 Wake-up from Sleep ..................................................... 55, 68 Interrupts......
PIC16F716 NOTES: DS41206A-page 122 Preliminary 2003 Microchip Technology Inc.
PIC16F716 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device PIC16F716, PIC16F716T, VDD range 2.0V to 5.5V Temperature Range I E = -40°C to +85°C = -40°C to +125°C Package SO P SS = = = Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) PIC16F716 -I/P 301= Industrial temp.
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