Datasheet

 2003 Microchip Technology Inc. Preliminary DS41206A-page 67
PIC16F716
9.10.1 INT INTERRUPT
External interrupt on RB0/INT pin is edge triggered,
either rising if bit INTEDG (OPTION_REG<6>) is set,
or falling if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service
routine before re-enabling this interrupt. The INT
interrupt can wake-up the processor from Sleep, if bit
INTE was set prior to going into Sleep. The status of
global interrupt enable bit GIE decides whether or not
the processor branches to the interrupt vector following
wake-up. See Section 9.13 “Power-down Mode
(Sleep)” for details on Sleep mode.
9.10.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 4.0 “Timer0 Module”).
9.10.3 PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 3.2 “PORTB and the TRISB Register”).
9.11 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt, (i.e., W register and Status
register). This will have to be implemented in firmware.
Example 9-1 stores and restores the W, Status,
PCLATH and FSR registers. Context storage registers,
W_TEMP, STATUS_TEMP, PCLATH_TEMP and
FSR_TEMP, must be defined in Common RAM which
are those addresses between 70h-7Fh in Bank 0 and
between F0h-FFh in Bank 1.
The example:
a) Stores the W register.
b) Stores the Status register in Bank 0.
c) Stores the PCLATH register
d) Stores the FSR register.
e) Executes the interrupt service routine code
(User-generated).
f) Restores all saved registers in reverse order
from which they were stored
EXAMPLE 9-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF W_TEMP ;Copy W to TEMP register, could be bank one or zero
SWAPF STATUS,W ;Swap status to be saved into W
MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register
MOVF PCLATH, W ;Only required if using pages 1, 2 and/or 3
MOVWF PCLATH_TEMP ;Save PCLATH into W
CLRF PCLATH ;Page zero, regardless of current page
BCF STATUS, IRP ;Return to Bank 0
MOVF FSR, W ;Copy FSR to W
MOVWF FSR_TEMP ;Copy FSR from W to FSR_TEMP
:
:(ISR)
:
MOVF FSR_TEMP,W ;Restore FSR
MOVWF FSR ;Move W into FSR
MOVF PCLATH_TEMP, W ;Restore PCLATH
MOVWF PCLATH ;Move W into PCLATH
SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W
MOVWF STATUS ;Move W into STATUS register
SWAPF W_TEMP,F ;Swap W_TEMP
SWAPF W_TEMP,W ;Swap W_TEMP into W
RETFIE ;Return from interrupt and enable GIE