Datasheet

 2003 Microchip Technology Inc. Preliminary DS41206A-page 43
PIC16F716
7.4.3 FULL-BRIDGE MODE
In Full-Bridge Output mode, four pins are used as
outputs; however, only two outputs are active at a time.
In the Forward mode, pin RB3/CCP1/P1A is
continuously active, and pin RB7/P1D is modulated. In
the Reverse mode, RB6/P1C pin is continuously active,
and RB5/P1B pin is modulated. These are illustrated in
Figure 7-6 through Figure 7-9.
P1A, P1B, P1C and P1D outputs are multiplexed with
the PORTB<3> and PORTB<5:7> data latches. The
TRISB<3> and TRISB<5:7> bits must be cleared to
make the P1A, P1B, P1C, and P1D pins output.
FIGURE 7-12: EXAMPLE OF FULL-BRIDGE APPLICATION
7.4.3.1 Direction Change in Full-Bridge
Mode
In the Full-Bridge Output mode, the P1M1 bit in the
CCP1CON register allows the user to control the
Forward/Reverse direction. When the application
firmware changes this direction control bit, the module
will assume the new direction on the next PWM cycle.
Just before the end of the current PWM period, the
modulated outputs (P1B and P1D) are placed in their
inactive state, while the unmodulated outputs (P1A and
P1C) are switched to drive in the opposite direction. This
occurs in a time interval of (4
•TOSC•(Timer2 Prescale
value)) before the next PWM period begins. The Timer2
prescaler will be either 1, 4 or 16, depending on the
value of the T2CKPSx bits (T2CON<1:0>). During the
interval from the switch of the unmodulated outputs to
the beginning of the next period, the modulated outputs
(P1B and P1D) remain inactive. This relationship is
shown in Figure 7-13.
PIC16F716
P1A
P1C
FET
Driver
FET
Driver
V+
V-
Load
FET
Driver
FET
Driver
P1B
P1D
QA
QB
QD
QC
Note: In the Full-Bridge Output mode, the ECCP
module does not provide any dead-band
delay. In general, since only one output is
modulated at all times, dead-band delay is
not required. However, there is a situation
where a dead-band delay might be
required. This situation occurs when both
of the following conditions are true:
1. The direction of the PWM output
changes when the duty cycle of the
output is at or near 100%.
2. The turn off time of the power switch,
including the power device and driver
circuit, is greater than the turn on
time.