Datasheet
2003 Microchip Technology Inc. Preliminary DS41206A-page 35
PIC16F716
7.2.1 CCP1 PIN CONFIGURATION
The user must configure the RB3/CCP1/P1A pin as the
CCP1 output by clearing the TRISB<3> bit.
7.2.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or
Synchronized Counter mode if the ECCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
7.2.3 SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. Only a CCP interrupt is
generated (if enabled).
7.2.4 SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The special event trigger output of the ECCP resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The special event trigger output of the ECCP also starts
an A/D conversion (if the A/D module is enabled).
FIGURE 7-2: COMPARE MODE
OPERATION BLOCK
DIAGRAM
TABLE 7-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Note: Clearing the CCP1CON register will force
the RB3/CCP1/P1A compare output latch
to the default low level. This is not the
PORTB I/O data latch.
Note: The special event trigger from the ECCP
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
CCPR1H CCPR1L
TMR1H TMR1L
Comparator
QS
R
Output
Logic
Special Event Trigger
Set flag bit CCP1IF
(PIR1<2>)
match
RB3/CCP1/P1A
TRISB<3>
CCP1CON<3:0>
Mode Select
Output Enable
Pin
Note 1: Special event trigger will reset Timer1, but not set
interrupt flag bit TMR1IF (PIR1<0>), and set bit GO/
DONE
(ADCON0<2>) which starts an A/D
conversion.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR,
BOR
Value on
all other
Resets
0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1
— ADIF — — — CCP1IF TMR2IF TMR1IF -0-- -000 -0-- -000
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1register xxxx xxxx uuuu uuuu
10h T1CON
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON
P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
86h TRISB PORTB Data direction register 1111 1111 1111 1111
8Ch PIE1
— ADIE — — — CCP1IE TMR2IE TMR1IE -0-- -000 -0-- -000
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by Capture and Timer1.