Datasheet

 2003 Microchip Technology Inc. Preliminary DS41206A-page 33
PIC16F716
7.0 ENHANCED CAPTURE/
COMPARE/PWM (ECCP)
MODULE
The ECCP (Enhanced Capture/Compare/PWM)
module contains a 16-bit register, which can operate
as:
• 16-bit Capture register
• 16-bit Compare register
• PWM Master/Slave Duty Cycle register
Table 7-1 shows the timer resources of the ECCP
module modes.
Capture/Compare/PWM Register 1 (CCPR1) is
comprised of two 8-bit registers: CCPR1L (low byte)
and CCPR1H (high byte).
The CCP1CON register controls ECCP operation. All
the CCP1CON bits are readable and writable.
Additional information on the ECCP module is available
in the PICmicro
®
Mid-Range Reference Manual,
(DS33023).
TABLE 7-1: ECCP MODE - TIMER
RESOURCE
REGISTER 7-1: CCP1CON REGISTER (ADDRESS: 17h)
ECCP Mode Timer Resource
Capture Timer1
Compare Timer1
PWM Timer2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 7 bit 0
bit 7-6 P1M1:P1M0: PWM Output Configuration bits
CCP1M<3:2> =
00, 01, 10
xx = P1A assigned as Capture/Compare I/O. P1B, P1C, P1D assigned as Port pins.
CCP1M<3:2> =
11
00 = Single output, P1A modulated. P1B, P1C, P1D assigned as Port pins.
01 = Quad output forward. P1D modulated, P1A active. P1B and P1C inactive.
10 = Dual output. P1A, P1B modulated with dead-time control. P1C, P1D assigned as port pins.
11 = Quad output reverse. P1B modulated, P1C active. P1A and P1D inactive.
bit 5-4 DC1B1:DC1B0: PWM Least Significant bits
Capture mode: Unused
Compare mode: Unused
PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found
in CCPR1L.
bit 3-0 CCP1M3:CCP1M0: ECCP Mode Select bits
0000 = Capture/Compare/PWM off (resets ECCP module)
0001 = Unused (Reserved)
0010 = Compare mode, toggle output on match (CCP1IF bit is set)
0011 = Unused (Reserved)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set CCP1 output on match (CCP1IF bit is set)
1001 = Compare mode, clear CCP1 output on match (CCP1IF bit is set)
1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected)
1011 = Compare mode, trigger special event (CCP1IF bit is set, TMR1 is reset, and an A/D conversion is
started if the A/D module is enabled. CCP1 pin is unaffected).
1100 = PWM mode. P1A, P1C active-high; P1B, P1D active-high.
1101 = PWM mode. P1A, P1C active-high; P1B, P1D active-low.
1110 = PWM mode. P1A, P1C active-low; P1B, P1D active-high.
1111 = PWM mode. P1A, P1C active-low; P1B, P1D active-low.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown