Datasheet

 2010-2011 Microchip Technology Inc. DS41418B-page 9
PIC16(L)F707
VDD 11, 32 7, 28 7, 8, 28 7,
26
— — — — — — — — — VDD
Vss 12, 31 6, 29 6, 30,
31
6,
27
—— — — —————VSS
TABLE 1: 40/44-PIN ALLOCATION TABLE FOR PIC16F707/PIC16LF707
I/O
40-Pin PDIP
44-Pin TQFP
44-Pin QFN
40-Pin UQFN
ANSEL
A/D
DAC
Cap Sensor
Timers
CCP
AUSART
SSP
Interrupt
Pull-up
Basic
Note 1: Pull-up activated only with external MCLR configuration.
2: RC1 is the default pin location for CCP2. RB3 may be selected by changing the CCP2SEL bit in the APFCON register.
3: RA5 is the default pin location for SS
. RA0 may be selected by changing the SSSEL bit in the APFCON register.
4: PIC16F707 only. V
CAP functionality is selectable by the VCAPEN bits in Configuration Word 2.