Datasheet

PIC16(L)F707
DS41418B-page 8 2010-2011 Microchip Technology Inc.
TABLE 1: 40/44-PIN ALLOCATION TABLE FOR PIC16F707/PIC16LF707
I/O
40-Pin PDIP
44-Pin TQFP
44-Pin QFN
40-Pin UQFN
ANSEL
A/D
DAC
Cap Sensor
Timers
CCP
AUSART
SSP
Interrupt
Pull-up
Basic
RA0 2 19 19 17 Y AN0
SS
(3)
VCAP
(4)
RA1 3 20 20 18 Y AN1 CPSA0
RA2 4 21 21 19 Y AN2 DACOUT CPSA1
RA3 5 22 22 20 Y AN3/
V
REF
VREF CPSA2
RA4 6 23 23 21 Y CPSA3 T0CKI/
TACKI
RA5 7 24 24 22 Y AN4 CPSA4 SS
(3)
——VCAP
(4)
RA6 14 31 33 29 Y CPSB1 OSC2/
CLKOUT/
V
CAP
(4)
RA7 13 30 32 28 Y CPSB0 OSC1/
CLKIN
RB0 33 8 9 8 Y AN12 CPSB8 IOC/INT Y
RB1 34 9 10 9 Y AN10 CPSB9 IOC Y
RB2 35 10 11 10 Y AN8 CPSB10 IOC Y
RB3 36 11 12 11 Y AN9 CPSB11 CCP2
(2)
——IOCY
RB4 37 14 14 12 Y AN11 CPSB12 IOC Y
RB5 38 15 15 13 Y AN13 CPSB13 T1G/
T3CKI
——IOCY
RB6 39 16 16 14 Y CPSB14 IOC Y ICSPCLK/
ICDCLK
RB7 40 17 17 15 Y CPSB15 IOC Y ICSPDAT/
ICDDAT
RC0 15 32 34 30 Y CPSB2 T1OSO/
T1CKI
RC1 16 35 35 31 Y CPSB3 T1OSI CCP2
(2)
——
RC2 17 36 36 32 Y CPSB4 TBCKI CCP1
RC3 18 37 37 33 SCK/
SCL
——
RC4 23 42 42 38 SDI/
SDA
RC5 24 43 43 39 Y CPSA9 SDO
RC6 25 44 44 40 Y CPSA10 TX/CK
RC7 26 1 1 1 Y CPSA11 RX/DT
RD0 19 38 38 34 Y CPSB5 T3G
RD1 20 39 39 35 Y CPSB6
RD2 21 40 40 36 Y CPSB7
RD3 22 41 41 37 Y CPSA8
RD4 27 2 2 2 Y CPSA12
RD5 28 3 3 3 Y CPSA13
RD6 29 4 4 4 Y CPSA14
RD7 30 5 5 5 Y CPSA15
RE0 8 25 25 23 Y AN5 CPSA5
RE1 9 26 26 24 Y AN6 CPSA6
RE2 10 27 27 25 Y AN7 CPSA7
RE3 1 18 18 16 Y
(1)
MCLR/
V
PP
Note 1: Pull-up activated only with external MCLR configuration.
2: RC1 is the default pin location for CCP2. RB3 may be selected by changing the CCP2SEL bit in the APFCON register.
3: RA5 is the default pin location for SS. RA0 may be selected by changing the SSSEL bit in the APFCON register.
4: PIC16F707 only. V
CAP functionality is selectable by the VCAPEN bits in Configuration Word 2.