Datasheet

PIC16(L)F707
DS41418B-page 48  2010-2011 Microchip Technology Inc.
4.5.5 PIR2 REGISTER
The PIR2 register contains the interrupt flag bits, as
shown in Register 4-5.
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 4-5: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0
TMR3GIF TMR3IF TMRBIF TMRAIF — — — CCP2IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 TMR3GIF: Timer3 Gate Interrupt Flag bit
1 = Timer3 gate is inactive
0 = Timer3 gate is active
bit 6 TMR3IF: Timer3 Overflow Interrupt Flag bit
1 = Timer3 register overflowed (must be cleared in software)
0 = Timer3 register did not overflow
bit 5 TMRBIF: TimerB Overflow Interrupt Flag bit
1 = TimerB register has overflowed (must be cleared in software)
0 = TimerB register did not overflow
bit 4 TMRAIF: TimerA Overflow Interrupt Flag bit
1 = TimerA register has overflowed (must be cleared in software)
0 = TimerA register did not overflow
bit 3-1 Unimplemented: Read as ‘0’
bit 0 CCP2IF: CCP2 Interrupt Flag bit
Capture Mode
1 = A Timer1 register capture occurred (must be cleared in software)
0 = No Timer1 register capture occurred
Compare Mode
1 = A Timer1 register compare match occurred (must be cleared in software)
0 = No Timer1 register compare match occurred
PWM Mode
Unused in this mode