Datasheet

PIC16(L)F707
DS41418B-page 46  2010-2011 Microchip Technology Inc.
4.5.3 PIE2 REGISTER
The PIE2 register contains the interrupt enable bits, as
shown in Register 4-3.
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 4-3: PIE2 – PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0
TMR3GIE TMR3IE TMRBIE TMRAIE — — — CCP2IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other
Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 TMR3GIE: Timer3 Gate Interrupt Flag bit
1 = Enable the Timer3 gate acquisition complete interrupt
0 = Disable the Timer3 gate acquisition complete interrupt
bit 6 TMR3IE: Timer3 Overflow Interrupt Enable bit
1 = Enables the Timer3 overflow interrupt
0 = Disables the Timer3 overflow interrupt
bit 5 TMRBIE: TimerB Overflow Interrupt Enable bit
1 = Enables the TimerB interrupt
0 = Disables the TimerB interrupt
bit 4 TMRAIE: TimerA Overflow Interrupt Enable bit
1 = Enables the TimerA interrupt
0 = Disables the TimerA interrupt
bit 3-1 Unimplemented: Read as '0'
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt