Datasheet

 2010-2011 Microchip Technology Inc. DS41418B-page 41
PIC16(L)F707
4.0 INTERRUPTS
The PIC16(L)F707 device family features an
interruptible core, allowing certain events to preempt
normal program flow. An Interrupt Service Routine
(ISR) is used to determine the source of the interrupt
and act accordingly. Some interrupts can be configured
to wake the MCU from Sleep mode.
The PIC16F707 family has 16 interrupt sources,
differentiated by corresponding interrupt enable and
flag bits:
• Timer0 Overflow Interrupt
• External Edge Detect on INT Pin Interrupt
• PORTB Change Interrupt
• Timer1 Gate Interrupt
• A/D Conversion Complete Interrupt
• AUSART Receive Interrupt
• AUSART Transmit Interrupt
• SSP Event Interrupt
• CCP1 Event Interrupt
• Timer2 Match with PR2 Interrupt
• Timer1 Overflow Interrupt
• CCP2 Event Interrupt
• TimerA Overflow Interrupt
• TimerB Overflow Interrupt
• Timer3 Overflow Interrupt
• Timer3 Gate Interrupt
A block diagram of the interrupt logic is shown in
Figure 4-1.
FIGURE 4-1: INTERRUPT LOGIC
TMR0IF
TMR0IE
INTF
INTE
RBIF
RBIE
GIE
PEIE
Wake-up (If in Sleep mode)
(1)
Interrupt to CPU
TMR1GIE
TMR1GIF
ADIF
ADIE
IOC-RB0
IOCB0
IOC-RB1
IOCB1
IOC-RB2
IOCB2
IOC-RB3
IOCB3
CCP1IF
CCP1IE
IOC-RB4
IOCB4
IOC-RB5
IOCB5
IOC-RB6
IOCB6
IOC-RB7
IOCB7
RCIF
RCIE
TMR2IE
TMR2IF
SSPIE
SSPIF
TXIE
TXIF
TMR1IE
TMR1IF
Note 1: Some peripherals depend upon the
system clock for operation. Since the
system clock is suspended during
Sleep, these peripherals will not wake
the part from Sleep. See Section 21.1
“Wake-up from Sleep”.
CCP2IF
CCP2IE
TMRAIF
TMRAIE
TMR3IF
TMR3IE
TMR3GIF
TMR3GIE
TMRBIF
TMRBIE