Datasheet

 2010-2011 Microchip Technology Inc. DS41418B-page 285
PIC16(L)F707
Specifications............................................................222
Timer1...............................................................................101
Asynchronous Counter Mode ................................... 104
Reading and Writing ......................................... 104
Modes of Operation .................................................. 103
Oscillator................................................................... 104
Prescaler...................................................................104
Specifications............................................................222
TMR1H Register .......................................................101
TMR1L Register........................................................101
Timer2
Associated registers.................................................. 118
Timers
Timer2
T2CON.............................................................. 118
Timing Diagrams
A/D Conversion......................................................... 224
A/D Conversion (Sleep Mode) .................................. 225
Asynchronous Reception.......................................... 146
Asynchronous Transmission..................................... 142
Asynchronous Transmission (Back-to-Back)............ 143
Brown-out Reset (BOR)............................................ 220
Brown-out Reset Situations ........................................35
CLKOUT and I/O.......................................................218
Clock Synchronization ..............................................177
Clock Timing .............................................................215
Enhanced Capture/Compare/PWM (ECCP) ............. 223
I
2
C Bus Data.............................................................230
I
2
C Bus Start/Stop Bits.............................................. 229
I
2
C Reception (7-bit Address)...................................172
I
2
C Slave Mode with SEN = 0 (Reception,
10-bit Address) ................................................. 173
I
2
C Transmission (7-bit Address).............................. 174
INT Pin Interrupt.......................................................... 42
Reset, WDT, OST and Power-up Timer ................... 220
Slave Select Synchronization ...................................165
SPI Master Mode ...................................................... 162
SPI Master Mode (CKE = 1, SMP = 1) ..................... 227
SPI Mode (Slave Mode with CKE = 0)...................... 164
SPI Mode (Slave Mode with CKE = 1)...................... 164
SPI Slave Mode (CKE = 0) ....................................... 227
SPI Slave Mode (CKE = 1) ....................................... 228
Synchronous Reception (Master Mode, SREN) ....... 155
Synchronous Transmission....................................... 153
Synchronous Transmission (Through TXEN) ........... 153
Time-out Sequence
Case 1 ................................................................ 36
Case 2 ................................................................ 37
Case 3 ................................................................ 37
Timer0 and Timer1 External Clock ........................... 222
USART Synchronous Receive (Master/Slave) .........226
USART Synchronous Transmission (Master/Slave) . 225
Wake-up from Interrupt............................................. 186
Timing Parameter Symbology...........................................214
Timing Requirements
I
2
C Bus Data.............................................................231
I2C Bus Start/Stop Bits.............................................230
SPI Mode .................................................................. 229
TMR0 Register....................................................................21
TMR1H Register ........................................................... 21, 22
TMR1L Register............................................................ 21, 22
TMR2 Register....................................................................21
TMRO Register ................................................................... 23
TRISA .................................................................................54
TRISA Register.............................................................22, 54
TRISB ................................................................................. 57
TRISB Register............................................................. 22, 58
TRISC................................................................................. 61
TRISC Register............................................................. 22, 61
TRISD................................................................................. 64
TRISD Register............................................................. 22, 65
TRISE ................................................................................. 67
TRISE Register............................................................. 22, 68
TXREG ............................................................................. 141
TXREG Register................................................................. 21
TXSTA Register.......................................................... 22, 147
BRGH Bit.................................................................. 149
U
UA..................................................................................... 179
Update Address bit, UA .................................................... 179
USART
Synchronous Master Mode
Requirements, Synchronous Receive .............. 226
Requirements, Synchronous Transmission...... 225
Timing Diagram, Synchronous Receive ........... 226
Timing Diagram, Synchronous Transmission... 225
V
VREF. SEE ADC Reference Voltage
W
Wake-up Using Interrupts................................................. 186
Watchdog Timer (WDT)...................................................... 33
Clock Source .............................................................. 33
Modes......................................................................... 34
Period ......................................................................... 33
Specifications ........................................................... 221
WCOL bit.................................................................. 166, 178
WPUB Register................................................................... 58
Write Collision Detect bit (WCOL) ............................ 166, 178
WWW Address ................................................................. 287
WWW, On-Line Support ..................................................... 11